Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:txq
394 	error = iwi_alloc_tx_ring(sc, &sc->txq[0], IWI_TX_RING_COUNT,
401 	error = iwi_alloc_tx_ring(sc, &sc->txq[1], IWI_TX_RING_COUNT,
408 	error = iwi_alloc_tx_ring(sc, &sc->txq[2], IWI_TX_RING_COUNT,
415 	error = iwi_alloc_tx_ring(sc, &sc->txq[3], IWI_TX_RING_COUNT,
467 	iwi_free_tx_ring(sc, &sc->txq[0]);
468 	iwi_free_tx_ring(sc, &sc->txq[1]);
469 	iwi_free_tx_ring(sc, &sc->txq[2]);
470 	iwi_free_tx_ring(sc, &sc->txq[3]);
1433 iwi_tx_intr(struct iwi_softc *sc, struct iwi_tx_ring *txq)
1442 	hw = CSR_READ_4(sc, txq->csr_ridx);
1444 	for (; txq->next != hw;) {
1445 		data = &txq->data[txq->next];
1455 		DPRINTFN(15, ("tx done idx=%u\n", txq->next));
1459 		txq->queued--;
1460 		txq->next = (txq->next + 1) % txq->count;
1465 	if (txq->queued < txq->count - 8 - 8 && (ifp->if_flags & IFF_OACTIVE)) {
1531 		iwi_tx_intr(sc, &sc->txq[0]);
1534 		iwi_tx_intr(sc, &sc->txq[1]);
1537 		iwi_tx_intr(sc, &sc->txq[2]);
1540 		iwi_tx_intr(sc, &sc->txq[3]);
1606 	struct iwi_tx_ring *txq = &sc->txq[ac];
1658 	data = &txq->data[txq->cur];
1659 	desc = &txq->desc[txq->cur];
1746 	bus_dmamap_sync(sc->sc_dmat, txq->desc_map,
1747 	    txq->cur * IWI_TX_DESC_SIZE,
1753 	DPRINTFN(5, ("sending data frame txq=%u idx=%u len=%u nseg=%u\n",
1754 	    ac, txq->cur, le16toh(desc->len), le32toh(desc->nseg)));
1757 	txq->queued++;
1758 	txq->cur = (txq->cur + 1) % txq->count;
1759 	CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
1806 		if (sc->txq[ac].queued > sc->txq[ac].count - 8) {
2754 	CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq[0].desc_map->dm_segs[0].ds_addr);
2755 	CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq[0].count);
2756 	CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq[0].cur);
2758 	CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq[1].desc_map->dm_segs[0].ds_addr);
2759 	CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq[1].count);
2760 	CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq[1].cur);
2762 	CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq[2].desc_map->dm_segs[0].ds_addr);
2763 	CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq[2].count);
2764 	CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq[2].cur);
2766 	CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq[3].desc_map->dm_segs[0].ds_addr);
2767 	CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq[3].count);
2768 	CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq[3].cur);
2929 	iwi_reset_tx_ring(sc, &sc->txq[0]);
2930 	iwi_reset_tx_ring(sc, &sc->txq[1]);
2931 	iwi_reset_tx_ring(sc, &sc->txq[2]);
2932 	iwi_reset_tx_ring(sc, &sc->txq[3]);
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