Lines Matching refs:ops
137 phy->ops.init = ixgbe_init_phy_ops_82598;
140 mac->ops.start_hw = ixgbe_start_hw_82598;
141 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;
142 mac->ops.reset_hw = ixgbe_reset_hw_82598;
143 mac->ops.get_media_type = ixgbe_get_media_type_82598;
144 mac->ops.get_supported_physical_layer =
146 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
147 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
148 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
149 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;
152 mac->ops.set_vmdq = ixgbe_set_vmdq_82598;
153 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;
154 mac->ops.set_vfta = ixgbe_set_vfta_82598;
155 mac->ops.set_vlvf = NULL;
156 mac->ops.clear_vfta = ixgbe_clear_vfta_82598;
159 mac->ops.fc_enable = ixgbe_fc_enable_82598;
170 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;
171 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;
174 mac->ops.check_link = ixgbe_check_mac_link_82598;
175 mac->ops.setup_link = ixgbe_setup_mac_link_82598;
176 mac->ops.flap_tx_laser = NULL;
177 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;
178 mac->ops.setup_rxpba = ixgbe_set_rxpba_82598;
181 mac->ops.set_fw_drv_ver = NULL;
183 mac->ops.get_rtrup2tc = NULL;
207 phy->ops.identify(hw);
210 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
211 mac->ops.setup_link = ixgbe_setup_copper_link_82598;
212 mac->ops.get_link_capabilities =
218 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
219 phy->ops.check_link = ixgbe_check_phy_link_tnx;
220 phy->ops.get_firmware_version =
224 phy->ops.reset = ixgbe_reset_phy_nl;
227 ret_val = phy->ops.identify_sfp(hw);
451 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
621 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
665 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
666 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
667 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
679 hw->phy.ops.read_reg(hw, 0xC79F,
682 hw->phy.ops.read_reg(hw, 0xC00C,
800 status = hw->phy.ops.setup_link_speed(hw, speed,
829 status = hw->mac.ops.stop_adapter(hw);
838 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
841 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
844 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
847 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
850 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
853 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
856 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
859 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
862 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
868 /* PHY ops must be identified and initialized prior to reset */
871 phy_status = hw->phy.ops.init(hw);
876 hw->phy.ops.reset(hw);
930 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
936 hw->mac.ops.init_rx_addrs(hw);
1148 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
1159 hw->phy.ops.write_reg_mdi(hw,
1166 hw->phy.ops.read_reg_mdi(hw,
1183 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1192 hw->mac.ops.release_swfw_sync(hw, gssr);
1242 hw->phy.ops.identify(hw);
1249 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1290 hw->phy.ops.identify_sfp(hw);
1347 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1350 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
Indexes created Mon Oct 13 04:09:54 GMT 2025