Lines Matching refs:hw
47 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
48 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
49 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
50 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
51 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
52 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
54 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
55 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
56 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
57 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
59 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
60 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
62 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
64 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
66 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
71 * @hw: pointer to the hardware structure
75 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
77 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
78 struct ixgbe_mac_info *mac = &hw->mac;
79 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
163 * @hw: pointer to hardware structure
169 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
177 switch (hw->phy.media_type) {
182 switch (hw->device_id) {
190 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
201 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
208 switch (hw->device_id) {
233 * @hw: pointer to hardware structure
237 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
247 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
258 if (hw->fc.requested_mode == ixgbe_fc_default)
259 hw->fc.requested_mode = ixgbe_fc_full;
263 * HW will be able to do fc autoneg once the cable is plugged in. If
266 switch (hw->phy.media_type) {
269 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
298 switch (hw->fc.requested_mode) {
302 if (hw->phy.media_type == ixgbe_media_type_backplane)
305 else if (hw->phy.media_type == ixgbe_media_type_copper)
315 if (hw->phy.media_type == ixgbe_media_type_backplane) {
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
336 if (hw->phy.media_type == ixgbe_media_type_backplane)
339 else if (hw->phy.media_type == ixgbe_media_type_copper)
350 if (hw->mac.type < ixgbe_mac_X540) {
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
359 if (hw->fc.strict_ieee)
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
371 if (hw->phy.media_type == ixgbe_media_type_backplane) {
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
377 (ixgbe_device_supports_autoneg_fc(hw))) {
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
389 * @hw: pointer to hardware structure
396 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
410 hw->mac.ops.clear_vfta(hw);
413 hw->mac.ops.clear_hw_cntrs(hw);
416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
419 IXGBE_WRITE_FLUSH(hw);
422 ret_val = ixgbe_setup_fc(hw);
429 switch (hw->mac.type) {
433 hw->mac.ops.get_device_caps(hw, &device_caps);
435 hw->need_crosstalk_fix = FALSE;
437 hw->need_crosstalk_fix = TRUE;
440 hw->need_crosstalk_fix = FALSE;
445 hw->adapter_stopped = FALSE;
452 * @hw: pointer to hw structure
460 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
468 for (i = 0; i < hw->mac.max_tx_queues; i++) {
469 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
470 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
472 IXGBE_WRITE_FLUSH(hw);
475 for (i = 0; i < hw->mac.max_tx_queues; i++) {
476 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
478 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
481 for (i = 0; i < hw->mac.max_rx_queues; i++) {
482 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
485 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
491 * @hw: pointer to hardware structure
499 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
506 status = hw->mac.ops.reset_hw(hw);
509 /* Start the HW */
510 status = hw->mac.ops.start_hw(hw);
514 if (hw->mac.ops.init_led_link_act)
515 hw->mac.ops.init_led_link_act(hw);
518 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
525 * @hw: pointer to hardware structure
530 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
536 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
537 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
538 IXGBE_READ_REG(hw, IXGBE_ERRBC);
539 IXGBE_READ_REG(hw, IXGBE_MSPDC);
540 if (hw->mac.type >= ixgbe_mac_X550)
541 IXGBE_READ_REG(hw, IXGBE_MBSDC);
543 IXGBE_READ_REG(hw, IXGBE_MPC(i));
545 IXGBE_READ_REG(hw, IXGBE_MLFC);
546 IXGBE_READ_REG(hw, IXGBE_MRFC);
547 if (hw->mac.type == ixgbe_mac_X550EM_a)
548 IXGBE_READ_REG(hw, IXGBE_LINK_DN_CNT);
549 IXGBE_READ_REG(hw, IXGBE_RLEC);
550 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
551 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
554 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
556 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
557 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
561 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
562 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
563 if (hw->mac.type >= ixgbe_mac_82599EB) {
564 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
565 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
567 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
568 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
571 if (hw->mac.type >= ixgbe_mac_82599EB)
573 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
574 IXGBE_READ_REG(hw, IXGBE_PRC64);
575 IXGBE_READ_REG(hw, IXGBE_PRC127);
576 IXGBE_READ_REG(hw, IXGBE_PRC255);
577 IXGBE_READ_REG(hw, IXGBE_PRC511);
578 IXGBE_READ_REG(hw, IXGBE_PRC1023);
579 IXGBE_READ_REG(hw, IXGBE_PRC1522);
580 IXGBE_READ_REG(hw, IXGBE_GPRC);
581 IXGBE_READ_REG(hw, IXGBE_BPRC);
582 IXGBE_READ_REG(hw, IXGBE_MPRC);
583 IXGBE_READ_REG(hw, IXGBE_GPTC);
584 IXGBE_READ_REG(hw, IXGBE_GORCL);
585 IXGBE_READ_REG(hw, IXGBE_GORCH);
586 IXGBE_READ_REG(hw, IXGBE_GOTCL);
587 IXGBE_READ_REG(hw, IXGBE_GOTCH);
588 if (hw->mac.type == ixgbe_mac_82598EB)
590 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
591 IXGBE_READ_REG(hw, IXGBE_RUC);
592 IXGBE_READ_REG(hw, IXGBE_RFC);
593 IXGBE_READ_REG(hw, IXGBE_ROC);
594 IXGBE_READ_REG(hw, IXGBE_RJC);
595 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
596 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
597 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
598 IXGBE_READ_REG(hw, IXGBE_TORL);
599 IXGBE_READ_REG(hw, IXGBE_TORH);
600 IXGBE_READ_REG(hw, IXGBE_TPR);
601 IXGBE_READ_REG(hw, IXGBE_TPT);
602 IXGBE_READ_REG(hw, IXGBE_PTC64);
603 IXGBE_READ_REG(hw, IXGBE_PTC127);
604 IXGBE_READ_REG(hw, IXGBE_PTC255);
605 IXGBE_READ_REG(hw, IXGBE_PTC511);
606 IXGBE_READ_REG(hw, IXGBE_PTC1023);
607 IXGBE_READ_REG(hw, IXGBE_PTC1522);
608 IXGBE_READ_REG(hw, IXGBE_MPTC);
609 IXGBE_READ_REG(hw, IXGBE_BPTC);
611 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
612 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
613 if (hw->mac.type >= ixgbe_mac_82599EB) {
614 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
615 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
616 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
617 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
618 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
620 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
621 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
625 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
626 if (hw->phy.id == 0)
627 ixgbe_identify_phy(hw);
628 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
630 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
632 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
634 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
643 * @hw: pointer to hardware structure
649 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
671 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
717 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
739 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
754 * @hw: pointer to hardware structure
759 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
766 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
776 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
788 * @hw: pointer to the HW structure
798 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
809 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
826 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
836 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
858 * @hw: pointer to the HW structure
867 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
876 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
894 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
916 * @hw: pointer to the HW structure
926 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
936 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
951 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
977 * @hw: pointer to hardware structure
984 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
992 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
993 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
1006 * @hw: pointer to hardware structure
1011 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1013 struct ixgbe_mac_info *mac = &hw->mac;
1015 if (hw->bus.type == ixgbe_bus_type_unknown)
1016 hw->bus.type = ixgbe_bus_type_pci_express;
1020 hw->bus.width = ixgbe_bus_width_pcie_x1;
1023 hw->bus.width = ixgbe_bus_width_pcie_x2;
1026 hw->bus.width = ixgbe_bus_width_pcie_x4;
1029 hw->bus.width = ixgbe_bus_width_pcie_x8;
1032 hw->bus.width = ixgbe_bus_width_unknown;
1038 hw->bus.speed = ixgbe_bus_speed_2500;
1041 hw->bus.speed = ixgbe_bus_speed_5000;
1044 hw->bus.speed = ixgbe_bus_speed_8000;
1047 hw->bus.speed = ixgbe_bus_speed_unknown;
1051 mac->ops.set_lan_id(hw);
1056 * @hw: pointer to hardware structure
1061 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1068 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1070 ixgbe_set_pci_config_data_generic(hw, link_status);
1077 * @hw: pointer to the HW structure
1083 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1085 struct ixgbe_bus_info *bus = &hw->bus;
1091 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1096 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1101 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1102 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1110 * @hw
1117 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1128 hw->adapter_stopped = TRUE;
1131 ixgbe_disable_rx(hw);
1142 * - hw->mac.ops.stop_adapter()
1148 * - hw->mac.ops.stop_adapter()
1154 ixgbe_ensure_disabled_intr(hw->back);
1157 IXGBE_READ_REG(hw, IXGBE_EICR);
1160 for (i = 0; i < hw->mac.max_tx_queues; i++)
1161 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1164 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1165 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1172 IXGBE_WRITE_FLUSH(hw);
1179 return ixgbe_disable_pcie_primary(hw);
1184 * @hw: pointer to hardware structure
1189 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1191 struct ixgbe_mac_info *mac = &hw->mac;
1195 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1212 switch (hw->mac.type) {
1225 * @hw: pointer to hardware structure
1228 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1230 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1240 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1241 IXGBE_WRITE_FLUSH(hw);
1248 * @hw: pointer to hardware structure
1251 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1253 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1263 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1264 IXGBE_WRITE_FLUSH(hw);
1271 * @hw: pointer to hardware structure
1276 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1278 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1296 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1324 * @hw: pointer to hardware structure
1331 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1339 hw->eeprom.ops.init_params(hw);
1346 if (offset + words > hw->eeprom.word_size) {
1355 if ((hw->eeprom.word_page_size == 0) &&
1357 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1367 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1380 * @hw: pointer to hardware structure
1388 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1400 status = ixgbe_acquire_eeprom(hw);
1403 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1404 ixgbe_release_eeprom(hw);
1411 ixgbe_standby_eeprom(hw);
1414 ixgbe_shift_out_eeprom_bits(hw,
1418 ixgbe_standby_eeprom(hw);
1424 if ((hw->eeprom.address_bits == 8) &&
1429 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1431 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1432 hw->eeprom.address_bits);
1434 page_size = hw->eeprom.word_page_size;
1440 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1451 ixgbe_standby_eeprom(hw);
1455 ixgbe_release_eeprom(hw);
1463 * @hw: pointer to hardware structure
1470 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1476 hw->eeprom.ops.init_params(hw);
1478 if (offset >= hw->eeprom.word_size) {
1483 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1491 * @hw: pointer to hardware structure
1498 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1506 hw->eeprom.ops.init_params(hw);
1513 if (offset + words > hw->eeprom.word_size) {
1527 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1540 * @hw: pointer to hardware structure
1547 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1558 status = ixgbe_acquire_eeprom(hw);
1561 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1562 ixgbe_release_eeprom(hw);
1569 ixgbe_standby_eeprom(hw);
1574 if ((hw->eeprom.address_bits == 8) &&
1579 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1581 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1582 hw->eeprom.address_bits);
1585 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1590 ixgbe_release_eeprom(hw);
1598 * @hw: pointer to hardware structure
1604 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1611 hw->eeprom.ops.init_params(hw);
1613 if (offset >= hw->eeprom.word_size) {
1618 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1626 * @hw: pointer to hardware structure
1633 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1642 hw->eeprom.ops.init_params(hw);
1650 if (offset >= hw->eeprom.word_size) {
1660 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1661 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1664 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1677 * @hw: pointer to hardware structure
1684 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1696 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1697 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1699 hw->eeprom.word_page_size = 0;
1703 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1711 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1714 hw->eeprom.word_page_size);
1721 * @hw: pointer to hardware structure
1727 hw, u16 offset, u16 *data)
1729 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1734 * @hw: pointer to hardware structure
1741 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1750 hw->eeprom.ops.init_params(hw);
1758 if (offset >= hw->eeprom.word_size) {
1769 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1775 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1777 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1790 * @hw: pointer to hardware structure
1796 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1798 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1803 * @hw: pointer to hardware structure
1809 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1819 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1821 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1839 * @hw: pointer to hardware structure
1844 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1852 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1857 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1861 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1864 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1873 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1876 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1884 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1885 IXGBE_WRITE_FLUSH(hw);
1894 * @hw: pointer to hardware structure
1898 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1930 ixgbe_release_eeprom_semaphore(hw);
1938 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1946 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1950 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1956 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1970 ixgbe_release_eeprom_semaphore(hw);
1984 * @hw: pointer to hardware structure
1988 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1994 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1998 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1999 IXGBE_WRITE_FLUSH(hw);
2004 * @hw: pointer to hardware structure
2006 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
2021 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
2023 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
2028 ixgbe_standby_eeprom(hw);
2045 * @hw: pointer to hardware structure
2047 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2053 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2057 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2058 IXGBE_WRITE_FLUSH(hw);
2061 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2062 IXGBE_WRITE_FLUSH(hw);
2068 * @hw: pointer to hardware structure
2072 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2081 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2102 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2103 IXGBE_WRITE_FLUSH(hw);
2107 ixgbe_raise_eeprom_clk(hw, &eec);
2108 ixgbe_lower_eeprom_clk(hw, &eec);
2119 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2120 IXGBE_WRITE_FLUSH(hw);
2125 * @hw: pointer to hardware structure
2128 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2143 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2149 ixgbe_raise_eeprom_clk(hw, &eec);
2151 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2157 ixgbe_lower_eeprom_clk(hw, &eec);
2165 * @hw: pointer to hardware structure
2168 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2177 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2178 IXGBE_WRITE_FLUSH(hw);
2184 * @hw: pointer to hardware structure
2187 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2196 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2197 IXGBE_WRITE_FLUSH(hw);
2203 * @hw: pointer to hardware structure
2205 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2211 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2216 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2217 IXGBE_WRITE_FLUSH(hw);
2223 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2225 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2228 msec_delay(hw->eeprom.semaphore_delay);
2233 * @hw: pointer to hardware structure
2237 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2250 if (hw->eeprom.ops.read(hw, i, &word)) {
2259 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2268 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2277 if (hw->eeprom.ops.read(hw, j, &word)) {
2292 * @hw: pointer to hardware structure
2298 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2311 status = hw->eeprom.ops.read(hw, 0, &checksum);
2317 status = hw->eeprom.ops.calc_checksum(hw);
2323 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2344 * @hw: pointer to hardware structure
2346 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2357 status = hw->eeprom.ops.read(hw, 0, &checksum);
2363 status = hw->eeprom.ops.calc_checksum(hw);
2369 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2402 * @hw: pointer to hardware structure
2410 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2414 u32 rar_entries = hw->mac.num_rar_entries;
2426 hw->mac.ops.set_vmdq(hw, index, vmdq);
2429 * HW expects these in little endian so we reverse the byte
2441 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2448 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2449 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2456 * @hw: pointer to hardware structure
2461 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2464 u32 rar_entries = hw->mac.num_rar_entries;
2480 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2483 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2484 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2487 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2494 * @hw: pointer to hardware structure
2500 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2503 u32 rar_entries = hw->mac.num_rar_entries;
2512 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2515 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2518 hw->mac.addr[0], hw->mac.addr[1],
2519 hw->mac.addr[2]);
2520 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2521 hw->mac.addr[4], hw->mac.addr[5]);
2526 hw->mac.addr[0], hw->mac.addr[1],
2527 hw->mac.addr[2]);
2528 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2529 hw->mac.addr[4], hw->mac.addr[5]);
2531 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2535 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2537 hw->addr_ctrl.overflow_promisc = 0;
2539 hw->addr_ctrl.rar_used_count = 1;
2544 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2545 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2549 hw->addr_ctrl.mta_in_use = 0;
2550 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2553 for (i = 0; i < hw->mac.mcft_size; i++)
2554 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2556 ixgbe_init_uta_tables(hw);
2563 * @hw: pointer to hardware structure
2569 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2571 u32 rar_entries = hw->mac.num_rar_entries;
2583 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2584 rar = hw->addr_ctrl.rar_used_count;
2585 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2587 hw->addr_ctrl.rar_used_count++;
2589 hw->addr_ctrl.overflow_promisc++;
2597 * @hw: pointer to hardware structure
2609 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2614 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2625 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2626 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2627 hw->addr_ctrl.overflow_promisc = 0;
2632 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2633 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2639 addr = next(hw, &addr_list, &vmdq);
2640 ixgbe_add_uc_addr(hw, addr, vmdq);
2643 if (hw->addr_ctrl.overflow_promisc) {
2645 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2647 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2649 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2653 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2655 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2657 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2667 * @hw: pointer to hardware structure
2677 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2683 switch (hw->mac.mc_filter_type) {
2709 * @hw: pointer to hardware structure
2714 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2722 hw->addr_ctrl.mta_in_use++;
2724 vector = ixgbe_mta_vector(hw, mc_addr);
2738 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2743 * @hw: pointer to hardware structure
2752 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2765 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2766 hw->addr_ctrl.mta_in_use = 0;
2771 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2777 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2781 for (i = 0; i < hw->mac.mcft_size; i++)
2782 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2783 hw->mac.mta_shadow[i]);
2785 if (hw->addr_ctrl.mta_in_use > 0)
2786 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2787 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2795 * @hw: pointer to hardware structure
2799 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2801 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2806 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2807 hw->mac.mc_filter_type);
2814 * @hw: pointer to hardware structure
2818 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2820 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2825 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2832 * @hw: pointer to hardware structure
2836 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2847 if (!hw->fc.pause_time) {
2854 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2855 hw->fc.high_water[i]) {
2856 if (!hw->fc.low_water[i] ||
2857 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2866 hw->mac.ops.fc_autoneg(hw);
2869 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2872 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2885 switch (hw->fc.current_mode) {
2889 * The code below will actually disable it in the HW.
2925 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2926 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2931 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2932 hw->fc.high_water[i]) {
2933 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2934 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2935 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2937 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2945 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2948 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2952 reg = (u32)hw->fc.pause_time * 0x00010001;
2954 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2957 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2965 * @hw: pointer to hardware structure
2976 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2995 if (hw->fc.requested_mode == ixgbe_fc_full) {
2996 hw->fc.current_mode = ixgbe_fc_full;
2999 hw->fc.current_mode = ixgbe_fc_rx_pause;
3004 hw->fc.current_mode = ixgbe_fc_tx_pause;
3008 hw->fc.current_mode = ixgbe_fc_rx_pause;
3011 hw->fc.current_mode = ixgbe_fc_none;
3019 * @hw: pointer to hardware structure
3023 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
3034 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3041 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3042 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3044 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3056 * @hw: pointer to hardware structure
3060 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3070 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3076 if (hw->mac.type == ixgbe_mac_82599EB) {
3077 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3087 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3088 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3090 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3100 * @hw: pointer to hardware structure
3104 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3109 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3112 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3116 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3124 * @hw: pointer to hardware structure
3129 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3143 if (hw->fc.disable_fc_autoneg) {
3150 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3156 switch (hw->phy.media_type) {
3162 ret_val = ixgbe_fc_autoneg_fiber(hw);
3167 ret_val = ixgbe_fc_autoneg_backplane(hw);
3172 if (ixgbe_device_supports_autoneg_fc(hw))
3173 ret_val = ixgbe_fc_autoneg_copper(hw);
3182 hw->fc.fc_was_autonegged = TRUE;
3184 hw->fc.fc_was_autonegged = FALSE;
3185 hw->fc.current_mode = hw->fc.requested_mode;
3191 * @hw: pointer to hardware structure
3199 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3204 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3238 * @hw: pointer to hardware structure
3245 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
3254 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3257 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3258 IXGBE_REMOVED(hw->hw_addr))
3264 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3277 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3279 if (hw->mac.type >= ixgbe_mac_X550)
3286 poll = ixgbe_pcie_timeout_poll(hw);
3289 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3290 if (IXGBE_REMOVED(hw->hw_addr))
3306 * @hw: pointer to hardware structure
3312 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3327 if (ixgbe_get_eeprom_semaphore(hw))
3330 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3333 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3334 ixgbe_release_eeprom_semaphore(hw);
3338 ixgbe_release_eeprom_semaphore(hw);
3345 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3353 * @hw: pointer to hardware structure
3359 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3366 ixgbe_get_eeprom_semaphore(hw);
3368 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3370 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3372 ixgbe_release_eeprom_semaphore(hw);
3377 * @hw: pointer to hardware structure
3379 * Stops the receive data path and waits for the HW to internally empty
3382 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3391 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3393 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3395 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3413 * @hw: pointer to hardware structure
3419 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3422 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3428 * @hw: pointer to hardware structure
3435 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3439 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3445 * @hw: pointer to hardware structure
3449 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3455 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3457 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3458 IXGBE_WRITE_FLUSH(hw);
3465 * @hw: pointer to hardware structure
3470 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3475 ixgbe_enable_rx(hw);
3477 ixgbe_disable_rx(hw);
3484 * @hw: pointer to hardware structure
3487 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3492 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3505 hw->mac.ops.check_link(hw
3508 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3515 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3519 IXGBE_WRITE_FLUSH(hw);
3525 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3526 IXGBE_WRITE_FLUSH(hw);
3534 * @hw: pointer to hardware structure
3537 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3540 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3549 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3556 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3563 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3564 IXGBE_WRITE_FLUSH(hw);
3572 * @hw: pointer to hardware structure
3579 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3590 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3603 * @hw: pointer to hardware structure
3611 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3623 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3628 hw->mac.ops.set_lan_id(hw);
3630 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3633 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3659 * @hw: pointer to hardware structure
3664 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3673 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3678 hw->mac.ops.set_lan_id(hw);
3680 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3686 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3695 * @hw: pointer to hardware structure
3700 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3706 switch (hw->mac.type) {
3724 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3725 if (IXGBE_REMOVED(hw->hw_addr))
3729 /* MSI-X count is zero-based in HW */
3740 * @hw: pointer to hardware structure
3747 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3757 /* swap bytes for HW little endian */
3769 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3770 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3776 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3782 if (rar < hw->mac.rar_highwater) {
3784 ixgbe_set_vmdq(hw, rar, vmdq);
3788 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3789 } else if (rar == hw->mac.rar_highwater) {
3791 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3792 hw->mac.rar_highwater++;
3793 } else if (rar >= hw->mac.num_rar_entries) {
3802 ixgbe_clear_vmdq(hw, rar, 0);
3809 * @hw: pointer to hardware struct
3813 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3816 u32 rar_entries = hw->mac.num_rar_entries;
3827 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3828 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3830 if (IXGBE_REMOVED(hw->hw_addr))
3838 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3839 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3842 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3843 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3850 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3855 rar != 0 && rar != hw->mac.san_mac_rar_index)
3856 hw->mac.ops.clear_rar(hw, rar);
3863 * @hw: pointer to hardware struct
3867 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3870 u32 rar_entries = hw->mac.num_rar_entries;
3882 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3886 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3897 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3900 * @hw: pointer to hardware struct
3903 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3905 u32 rar = hw->mac.san_mac_rar_index;
3910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3911 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3913 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3914 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3922 * @hw: pointer to hardware structure
3924 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3932 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3939 * @hw: pointer to hardware structure
3948 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3972 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3990 * @hw: pointer to hardware structure
3998 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4023 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
4036 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4054 * @hw: pointer to hardware structure
4065 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4084 hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4087 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4091 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4102 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4108 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4136 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4143 * @hw: pointer to hardware structure
4147 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4153 for (offset = 0; offset < hw->mac.vft_size; offset++)
4154 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4157 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4158 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4159 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4167 * @hw: pointer to hardware structure
4172 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
4184 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4205 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4207 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4208 IXGBE_WRITE_FLUSH(hw);
4211 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4213 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4214 IXGBE_WRITE_FLUSH(hw);
4222 * @hw: pointer to hardware structure
4227 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4231 if (!hw->need_crosstalk_fix)
4235 switch (hw->mac.ops.get_media_type(hw)) {
4248 * @hw: pointer to hardware structure
4255 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4266 if (ixgbe_need_crosstalk_fix(hw)) {
4267 if ((hw->mac.type != ixgbe_mac_82598EB) &&
4268 !ixgbe_sfp_cage_full(hw)) {
4276 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4278 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4286 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4294 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4298 if (ixgbe_need_crosstalk_fix(hw)) {
4304 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4321 if (hw->mac.type >= ixgbe_mac_X550) {
4331 if (hw->mac.type >= ixgbe_mac_X550) {
4338 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4339 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4352 * @hw: pointer to hardware structure
4359 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4373 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4382 if (hw->eeprom.ops.read(hw, offset, &caps))
4389 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4395 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4409 * @hw: pointer to hardware structure
4414 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4426 status = hw->eeprom.ops.read(hw, offset, &caps);
4434 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4443 status = hw->eeprom.ops.read(hw, offset, &flags);
4458 * @hw: pointer to hardware structure
4463 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4469 if (hw->mac.type == ixgbe_mac_82598EB)
4472 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4477 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4482 * @hw: pointer to hardware structure
4487 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4493 if (hw->mac.type == ixgbe_mac_82598EB)
4496 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4501 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4506 * @hw: pointer to hardware structure
4512 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4516 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4523 * @hw: pointer to hardware structure
4526 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4534 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4535 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4537 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4540 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4541 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4544 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4574 * @hw: pointer to the HW structure
4586 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4600 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4601 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4604 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4622 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4626 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4629 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4644 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4655 * @hw: pointer to the HW structure
4671 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4689 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4693 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4705 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4717 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4741 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4746 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4753 * @hw: pointer to the HW structure
4766 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 minr,
4780 fw_cmd.port_num = (u8)hw->bus.func;
4792 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4813 * @hw: pointer to hardware structure
4818 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4821 u32 pbsize = hw->mac.rx_pb_size;
4843 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4848 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4858 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4859 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4864 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4865 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4866 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4872 * @hw: pointer to the hardware structure
4878 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4887 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4895 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4896 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4899 IXGBE_WRITE_FLUSH(hw);
4906 poll = ixgbe_pcie_timeout_poll(hw);
4909 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4910 if (IXGBE_REMOVED(hw->hw_addr))
4918 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4919 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4923 IXGBE_WRITE_FLUSH(hw);
4927 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4935 * @hw: pointer to hardware structure
4941 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
4953 switch (hw->mac.type) {
4975 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4981 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4982 IXGBE_WRITE_FLUSH(hw);
4987 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4988 IXGBE_WRITE_FLUSH(hw);
4992 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4993 IXGBE_WRITE_FLUSH(hw);
5000 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5003 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5005 IXGBE_WRITE_FLUSH(hw);
5009 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5010 IXGBE_WRITE_FLUSH(hw);
5014 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5015 IXGBE_WRITE_FLUSH(hw);
5018 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5029 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5030 IXGBE_WRITE_FLUSH(hw);
5034 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5035 IXGBE_WRITE_FLUSH(hw);
5101 * @hw: pointer to hardware structure
5109 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5118 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5123 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5133 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5147 * @hw: pointer to hardware structure
5151 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5160 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5168 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5179 * @hw: pointer to hardware structure
5185 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5192 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5198 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5199 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5217 * @hw: pointer to hardware structure
5223 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5229 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5236 hw->eeprom.ops.read(hw, offset, &mod_len);
5237 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5244 hw->eeprom.ops.read(hw
5245 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5261 * @hw: pointer to hardware structure
5266 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5270 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5272 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5290 * @hw: pointer to hardware structure
5293 * Read the rtrup2tc HW register and resolve its content into map
5295 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5299 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5306 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5311 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5313 if (hw->mac.type != ixgbe_mac_82598EB) {
5314 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5317 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5318 hw->mac.set_lben = TRUE;
5320 hw->mac.set_lben = FALSE;
5324 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5328 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5333 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5334 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5336 if (hw->mac.type != ixgbe_mac_82598EB) {
5337 if (hw->mac.set_lben) {
5338 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5340 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5341 hw->mac.set_lben = FALSE;
5348 * @hw: pointer to hardware structure
5350 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5354 if (hw->mac.type < ixgbe_mac_82599EB)
5357 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5363 * @hw: pointer to hardware structure
5367 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5371 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5375 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5379 if (hw->mac.type <= ixgbe_mac_X540) {
5380 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5390 * @hw: pointer to hardware structure
5396 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5410 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5424 switch (hw->phy.media_type) {
5427 ixgbe_set_rate_select_speed(hw,
5441 status = ixgbe_setup_mac_link(hw,
5448 ixgbe_flap_tx_laser(hw);
5459 status = ixgbe_check_link(hw, &link_speed,
5475 switch (hw->phy.media_type) {
5478 ixgbe_set_rate_select_speed(hw,
5492 status = ixgbe_setup_mac_link(hw,
5499 ixgbe_flap_tx_laser(hw);
5505 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
5515 ixgbe_disable_tx_laser(hw);
5525 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5531 hw->phy.autoneg_advertised = 0;
5534 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5537 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5544 * @hw: pointer to hardware structure
5549 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5569 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5579 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5588 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5598 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
Indexes created Wed Oct 15 16:09:53 GMT 2025