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Lines Matching defs:reg_val

2325 	u32 reg_val;
2329 		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2333 	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2334 	reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2339 		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2343 		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2347 		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2353 				    IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2358 		reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2359 		reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2360 		reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2361 		reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2362 		reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2366 				    IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2810 	u16 reg_slice, reg_val;
2834 		reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2836 		reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2838 					  reg_val);
2854 	u32 reg_val;
2859 					IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2863 	reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2864 	reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2865 	reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2866 	reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2871 		reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2874 		reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2886 					IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3009 	u32 reg_val;
3014 				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3017 	reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
3020 				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3027 				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3030 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3031 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3032 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3035 				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3040 				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3043 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
3044 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
3045 	reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
3048 				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3055 				IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3058 	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
3059 	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
3060 	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
3061 	reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
3064 				IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3080 	u32 reg_val;
3089 					IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3093 	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3094 	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3099 		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3102 		reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
3111 					IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3238 	u32 reg_val;
3243 		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3246 	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
3247 	reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
3248 	reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
3251 		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3258 		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3261 	reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
3262 	reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
3265 		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3272 		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3275 	reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
3278 		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3285 		IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3288 	reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
3291 		IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
4103 	u32 pause, asm_dir, reg_val;
4157 			IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
4160 		reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
4163 			reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
4165 			reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
4168 			IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);