Lines Matching defs:onoff
818 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off")
861 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE);
862 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE);
863 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE);
864 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE);
865 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE);
866 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE);
867 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE);
868 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE);
869 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE);
870 onoff("Fast back-to-back transactions", rval,
872 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE);
875 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS);
878 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT);
879 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT);
880 onoff("User Definable Features (UDF) support", rval,
882 onoff("Fast back-to-back capable", rval,
884 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR);
903 onoff("Slave signaled Target Abort", rval,
905 onoff("Master received Target Abort", rval,
907 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT);
908 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR);
909 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT);
1202 onoff("SBA", rval, AGP_MODE_SBA);
1203 onoff("htrans#", rval, AGP_MODE_HTRANS);
1204 onoff("Over 4G", rval, AGP_MODE_4G);
1205 onoff("Fast Write", rval, AGP_MODE_FW);
1206 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3);
1219 onoff("SBA", rval, AGP_MODE_SBA);
1220 onoff("AGP", rval, AGP_MODE_AGP);
1221 onoff("Over 4G", rval, AGP_MODE_4G);
1222 onoff("Fast Write", rval, AGP_MODE_FW);
1276 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
1277 onoff("Device specific initialization", caps, PCI_PMCR_DSI);
1280 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
1281 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
1282 onoff("PME# support D0", caps, PCI_PMCR_PME_D0);
1283 onoff("PME# support D1", caps, PCI_PMCR_PME_D1);
1284 onoff("PME# support D2", caps, PCI_PMCR_PME_D2);
1285 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT);
1286 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD);
1290 onoff("PCI Express reserved", (pmcsr >> 2), 1);
1291 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST);
1298 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
1301 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT);
1302 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN);
1323 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE);
1328 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
1329 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
1330 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP);
1331 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN);
1421 onoff("64bit device", reg, PCIX_STATUS_64BIT);
1422 onoff("133MHz capable", reg, PCIX_STATUS_133);
1423 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1424 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1425 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1426 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1432 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266);
1433 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533);
1437 onoff("Data Parity Error Recovery", reg,
1439 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER);
1452 onoff("64bit device", reg, PCIX_STATUS_64BIT);
1453 onoff("133MHz capable", reg, PCIX_STATUS_133);
1454 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC);
1455 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX);
1457 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN);
1458 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL);
1470 onoff("Received split completion error", reg,
1473 onoff("266MHz capable", reg, PCIX_STATUS_266);
1474 onoff("533MHz capable", reg, PCIX_STATUS_533);
1511 onoff("Enable", val, PCI_HT_MSI_ENABLED);
1512 onoff("Fixed", val, PCI_HT_MSI_FIXED);
1650 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP);
1651 onoff("HyperTransport tunnel translation support", reg,
1653 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE);
1654 onoff("IOMMU Extended Feature Register support", reg,
1656 onoff("IOMMU Miscellaneous Information Register 1", reg,
1662 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
1673 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID);
1695 onoff("ATS response address range reserved", reg,
1946 onoff("Slot implemented", reg, PCIE_XCAP_SI);
1976 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON);
1977 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND);
1978 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND);
1979 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT);
1986 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR);
1991 onoff("Correctable Error Reporting Enable", reg,
1993 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER);
1994 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER);
1995 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR);
1996 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD);
1999 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD);
2000 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS);
2001 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM);
2002 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP);
2006 onoff("Bridge Config Retry Enable", reg,
2012 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED);
2013 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED);
2014 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED);
2015 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
2016 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
2017 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
2018 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD);
2049 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM);
2050 onoff("Surprise Down Error Report", reg,
2052 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE);
2053 onoff("Link BW Notification Capable", reg,
2055 onoff("ASPM Optionally Compliance", reg,
2078 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS);
2079 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN);
2080 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG);
2081 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC);
2082 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM);
2083 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD);
2084 onoff("Link Bandwidth Management Interrupt Enable", reg,
2086 onoff("Link Autonomous Bandwidth Interrupt Enable", reg,
2112 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR);
2113 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN);
2114 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG);
2115 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE);
2116 onoff("Link Bandwidth Management Status", reg,
2118 onoff("Link Autonomous Bandwidth Status", reg,
2128 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP);
2129 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP);
2130 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP);
2131 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP);
2132 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP);
2133 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS);
2134 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC);
2138 onoff("Electromechanical Interlock Present", reg,
2140 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS);
2147 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE);
2148 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE);
2149 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE);
2150 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE);
2151 onoff("Command Completed Interrupt Enabled", reg,
2153 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE);
2195 onoff("Electromechanical Interlock Control",
2197 onoff("Data Link Layer State Changed Enable", reg,
2199 onoff("Auto Slot Power Limit Disable", reg,
2204 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP);
2205 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD);
2206 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC);
2207 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC);
2208 onoff("Command Completed", reg, PCIE_SLCSR_CC);
2209 onoff("MRL Open", reg, PCIE_SLCSR_MS);
2210 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS);
2211 onoff("Electromechanical Interlock engaged", reg,
2213 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS);
2220 onoff("SERR on Correctable Error Enable", reg,
2222 onoff("SERR on Non-Fatal Error Enable", reg,
2224 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER);
2225 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE);
2226 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE);
2231 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV);
2238 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT);
2239 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND);
2262 onoff("Completion Timeout Disable Supported", reg,
2264 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD);
2265 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT);
2266 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM);
2267 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM);
2268 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS);
2269 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS);
2270 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC);
2301 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);
2302 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);
2318 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD);
2319 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
2337 onoff("Emergency Power Reduction Initialization Required", reg,
2339 onoff("FRS Supported", reg, PCIE_DCAP2_FRS);
2346 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS);
2347 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD);
2348 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ);
2349 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK);
2350 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
2351 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
2352 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
2353 onoff("Emergency Power Reduction Request", reg,
2355 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);
2371 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP);
2385 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK);
2396 onoff("Retimer Presence Detect Supported", reg,
2398 onoff("DRS Supported", reg, PCIE_LCAP2_DRS);
2409 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL);
2410 onoff("HW Autonomous Speed Disabled", reg,
2418 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP);
2419 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS);
2431 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL);
2432 onoff("Equalization Phase 1 Successful", reg,
2434 onoff("Equalization Phase 2 Successful", reg,
2436 onoff("Equalization Phase 3 Successful", reg,
2438 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ);
2439 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD);
2464 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV);
2484 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
2485 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
2535 onoff("Transaction Pending", reg, PCI_AF_TP_CAP);
2536 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP);
2544 onoff("Transaction Pending", reg, PCI_AFSR_TP);
2665 onoff("Writable", reg, PCI_EA_W);
2666 onoff("Enable for this entry", reg, PCI_EA_E);
2837 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED);
2838 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR);
2839 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR);
2840 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP);
2841 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR);
2842 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT);
2843 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT);
2844 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION);
2845 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW);
2846 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP);
2847 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR);
2848 onoff("Unsupported Request Error", reg,
2850 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION);
2851 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR);
2852 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP);
2853 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED);
2854 onoff("TLP Prefix Blocked Error", reg,
2856 onoff("Poisoned TLP Egress Blocked", reg,
2864 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR);
2865 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP);
2866 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP);
2867 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER);
2868 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT);
2869 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR);
2870 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR);
2871 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW);
2880 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE);
2881 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE);
2882 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE);
2883 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE);
2884 onoff("Multiple Header Recording Capable", reg,
2886 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE);
2887 onoff("Completion Timeout Prefix/Header Log Capable", reg,
2893 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT);
2901 onoff("Correctable Error Reporting Enable", reg,
2903 onoff("Non-Fatal Error Reporting Enable", reg,
2905 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE);
2912 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR);
2913 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR);
2914 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR);
2915 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg,
2917 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL);
2918 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR);
2919 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR);
3059 onoff("Hardware fixed arbitration scheme",
3061 onoff("WRR arbitration with 32 phases",
3063 onoff("WRR arbitration with 64 phases",
3065 onoff("WRR arbitration with 128 phases",
3077 onoff("VC Arbitration Table Status",
3088 onoff(" Non-configurable Hardware fixed arbitration scheme",
3090 onoff(" WRR arbitration with 32 phases",
3092 onoff(" WRR arbitration with 64 phases",
3094 onoff(" WRR arbitration with 128 phases",
3096 onoff(" Time-based WRR arbitration with 128 phases",
3098 onoff(" WRR arbitration with 256 phases",
3100 onoff(" Advanced Packet Switching",
3102 onoff(" Reject Snoop Transaction",
3124 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
3128 onoff(" Port Arbitration Table Status",
3130 onoff(" VC Negotiation Pending",
3255 onoff("System Allocated",
3298 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID);
3302 onoff(" Associated RCRB Header", reg,
3396 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V);
3397 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B);
3398 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R);
3399 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C);
3400 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U);
3401 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E);
3402 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T);
3408 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V);
3409 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B);
3410 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R);
3411 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C);
3412 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U);
3413 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E);
3414 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T);
3438 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M);
3439 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A);
3443 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M);
3444 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A);
3465 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ);
3466 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL);
3467 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD);
3472 onoff("Enable", reg, PCI_ATS_CTL_EN);
3502 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION);
3503 onoff("ARI Capable Hierarchy Preserved", reg,
3512 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE);
3513 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT);
3514 onoff("VF Migration Interrupt Enable", reg,
3516 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE);
3517 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER);
3521 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION);
3622 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
3627 onoff("Enable", reg, PCI_MCAST_CTL_ENA);
3679 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E);
3680 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R);
3683 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF);
3684 onoff("Unexpected Page Request Group Index", reg,
3686 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S);
3687 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR);
3810 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN);
3847 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
3848 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
3849 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
3850 onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
3937 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ);
3938 onoff("Link Equalization Request Interrupt Enable",
3991 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM);
3992 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE);
3997 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN);
3998 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN);
3999 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN);
4014 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64);
4015 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128);
4020 onoff("LNR Enable", reg, PCI_LNR_CTL_EN);
4021 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS);
4029 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL);
4030 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL);
4031 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO);
4032 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL);
4033 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL);
4034 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO);
4035 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL);
4036 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL);
4037 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO);
4056 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT);
4057 onoff("Poisoned TLP Egress Blocking Supported", reg,
4059 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG);
4062 onoff("DL_Active ERR_COR Signaling Supported", reg,
4083 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE);
4084 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN);
4085 onoff("Poisoned TLP Egress Blocking Enable", reg,
4087 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG);
4088 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR);
4094 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT);
4110 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT);
4112 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY);
4194 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12);
4195 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11);
4196 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12);
4197 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11);
4198 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM);
4204 onoff("Link Activation Supported", reg,
4220 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN);
4221 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN);
4222 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN);
4223 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN);
4224 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE);
4225 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA);
4246 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA);
4260 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ);
4261 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP);
4262 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT);
4279 onoff("PTM Enable", reg, PCI_PTM_CTL_EN);
4280 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL);
4310 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
4311 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG);
4315 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
4316 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID);
4335 onoff("Equalization 16.0 GT/s Complete", reg, PCI_PL16G_STAT_EQ_COMPL);
4336 onoff("Equalization 16.0 GT/s Phase 1 Successful", reg,
4338 onoff("Equalization 16.0 GT/s Phase 2 Successful", reg,
4340 onoff("Equalization 16.0 GT/s Phase 3 Successful", reg,
4447 onoff("Margining uses Driver Software", reg, PCI_LMR_PCAP_MUDS);
4449 onoff("Margining Ready", reg, PCI_LMR_PSTAT_MR);
4450 onoff("Margining Software Ready", reg, PCI_LMR_PSTAT_MSR);
4693 onoff("66 MHz capable", rval, __BIT(5));
4694 onoff("User Definable Features (UDF) support", rval, __BIT(6));
4695 onoff("Fast back-to-back capable", rval, __BIT(7));
4696 onoff("Data parity error detected", rval, __BIT(8));
4716 onoff("Signalled target abort", rval, __BIT(11));
4717 onoff("Received target abort", rval, __BIT(12));
4718 onoff("Received master abort", rval, __BIT(13));
4719 onoff("Received system error", rval, __BIT(14));
4720 onoff("Detected parity error", rval, __BIT(15));
4752 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE);
4872 onoff("32bit I/O", rval, use_upper);
4925 onoff("64bit memory address", rval, use_upper);
4981 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE);
4982 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
4983 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
4984 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA);
4991 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
4992 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
4993 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
4994 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B);
4995 onoff("Primary Discard Timer", rval,
4997 onoff("Secondary Discard Timer",
4999 onoff("Discard Timer Status", rval,
5001 onoff("Discard Timer SERR# Enable", rval,
5092 onoff("Parity error response", rval, __BIT(0));
5093 onoff("SERR# enable", rval, __BIT(1));
5094 onoff("ISA enable", rval, __BIT(2));
5095 onoff("VGA enable", rval, __BIT(3));
5096 onoff("Master abort mode", rval, __BIT(5));
5097 onoff("Secondary (CardBus) bus reset", rval, __BIT(6));
5098 onoff("Functional interrupts routed by ExCA registers", rval,
5100 onoff("Memory window 0 prefetchable", rval, __BIT(8));
5101 onoff("Memory window 1 prefetchable", rval, __BIT(9));
5102 onoff("Write posting enable", rval, __BIT(10));
Indexes created Fri Sep 26 08:10:20 GMT 2025