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History log of /src/sys/dev/pci/pci_subr.c
RevisionDateAuthorComments
 1.244  19-Apr-2024  andvar s/Resorce/Resource/ in comment and log message.
 1.243  10-Aug-2023  andvar fix typos in comments.
 1.242  01-Feb-2022  msaitoh Fix typo. Found by rillig. s/vendor specific/vendor-specific/
 1.241  31-Jan-2022  msaitoh Decode SCSI programming interface. Whitespace fix.
 1.240  31-Jan-2022  msaitoh Add three new extended capabilities:

- Physical Layer 32.0 GT/s
- Alternate Protocol
- System Firmware Intermediary
 1.239  08-Jan-2022  tnn place additional parens around multiline string constant to appease clang
 1.238  07-Jan-2022  msaitoh Two fixes:

- Fix previous again. The missing comma is intended to split the long line.
- Add missing right parenthesis.
 1.237  07-Jan-2022  msaitoh Add missing comma. Found by tnn@.
 1.236  01-Jan-2022  msaitoh Print Physical Layer 16.0 GT/s and Lane Margining at the Receiver extended cap.

- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Rename pcie_link_compliance_preset_deemphasis to
pcie_link_preset_preshoot_deemphasis because the table is referenced from
multiple places.
- Print "reserved" instead of "unknown" when printing equalization preset.
One of them is known to be the default value.
- Rename PCI_EXTCAP_PYSLAY_16GT to PCI_EXTCAP_PL16G.
 1.235  28-Dec-2021  msaitoh %hhx -> %x
 1.234  28-Dec-2021  msaitoh Decode link control2's Compliance Preset/De-emphasis more. Fix typo.
 1.233  03-Dec-2021  andvar fix various typos in comments, log messages and documentation.
 1.232  10-Oct-2021  msaitoh Use PCI-SIG official acronyms:

- RP stands for Root Port.
- RC stands for Root Complex.
- RCIEP stands for Root Complex Integrated End Point.
 1.231  10-Oct-2021  msaitoh Add Some PCI config information:

- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
 1.230  11-Sep-2021  mrg add 32.0GT/s to the list of pcie speeds (PCIe 5.x.)
 1.229  17-Aug-2021  andvar fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.
 1.228  17-Aug-2021  andvar s/Windw/Window/ in log message.
 1.227  12-Jul-2021  msaitoh s/Precision Time Management/Precision Time Measurement/
 1.226  29-Jun-2021  pgoyette Rework the xxxVERBOSE option to share the common module-hook-based
verbose mechanism with MIIVERBOSE. This reduces some duplicated code
and allows us to once again permit auto-unload of MIIVERBOSE.

Change details:
* Update dev/devlist2h.awk to accomodate miidevs, including generation
of MII_STR_oui_model definitions and use of oui and model rather than
vendor and product. This also changes the compressed data in the
xxxdevs_data.h files to uint32_t (since mii oui's are up to 6 hex
digits long)
* Update a couple of phy drivers to use new calls to get verbose data
* Regen all of the xxxdevs{,_data}.h files (separate commit, coming
very soon)
* Update mii/mii_verbose.[ch] and mii/mii_physubr.c to use the various
DEV_VERBOSE_xxx macros
* Update the pci, usb, and hdaudio code as needed, to #include the
xxxdevs.h files (in order to get the proper printf format strings)
* Since dev/dev_verbose.c now uses non-literal printf format strings,
(to deal with the vendor/product vs oui/model issue), we need to
make sure it gets compiled with -Wno-error=format-nonliteral, even
in userland's libpci and librumpdev!
* Bump kernel version for the change in module interfaces

Welcome to 9.99.86!

XXX It might be useful in the future to extend the MII_STR_oui_model
XXX definitions to PCI as well (and perhaps USB and HDAUDIO). This
XXX would allow for a single centralized location for the products'
XXX descriptions, rather than being dispersed among individual
XXX drivers' xxx_match tables.
 1.225  27-Jan-2021  thorpej branches: 1.225.4;
Introduce autoconfiguration helpers based around device_compatible_entry:
- pci_compatible_match(): matches against the PCI ID.
- pci_compatible_match_subsys(): matches against PCI SUBSYS ID.
- pci_compatible_lookup(): look up entry by PCI ID.
- pci_compatible_lookup_subsys(): look up entry by PCI SUBSYS ID.
- pci_compatible_lookup_id(): look up entry by an arbitrary ID using the
PCI ID code conventions.

- Define PCI_COMPAT_EOL as a compat data array sentinel.
 1.224  30-May-2020  jdolecek branches: 1.224.2;
change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack
 1.223  10-Apr-2020  christos Fix all the random __SHIFTOUT casts by introducing an intermediate macho,
and then deleting and fixing the rest.
 1.222  21-Mar-2020  thorpej branches: 1.222.2;
When parsing Enhanced Allocation entries, use the correct calulation for
finding the next entry.
 1.221  25-Jan-2020  msaitoh Add PCIe 4.0 stuff a little:

- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
 1.220  25-Jan-2020  msaitoh - Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.
 1.219  17-Jan-2020  msaitoh Fix a bug that the virtual channel extended configuraton's arbitration phase
register can't be decoded correcty. Found by jmcneill.
 1.218  11-Dec-2019  msaitoh branches: 1.218.2;
s/enalbe/enable/
 1.217  20-Sep-2019  msaitoh Print some DPC register values not with %04x but with %08x because those
are 32bit.
 1.216  21-Aug-2019  msaitoh Whitespace fixes. No functional change.
 1.215  18-Jul-2019  msaitoh branches: 1.215.2;
Remove whitespace for consistency.
 1.214  09-Jul-2019  msaitoh Print extend capability from 0x25 to 0x29 correctly.
 1.213  09-Jul-2019  msaitoh Identify 16GT/s.
 1.212  01-Mar-2019  msaitoh - Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.
 1.211  28-Feb-2019  khorben Typo (s/vaule/value/)
 1.210  30-Nov-2018  msaitoh Add new PCIE_HAS_LINKREGS(pcie_devtype) and use it. No functional change.
 1.209  30-Nov-2018  msaitoh Add new macro PCIE_HAS_ROOTREGS(pcie_devtype) and use it. No functional
change.
 1.208  30-Nov-2018  msaitoh The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:
 1.207  05-Nov-2018  msaitoh Decode PCI Enhanced Allocation.
 1.206  04-Oct-2018  msaitoh Don't print extra newline if the PCI extended configuration space doesn't exist.
 1.205  03-Oct-2018  msaitoh - Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicaple
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.
 1.204  27-Sep-2018  msaitoh Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.
 1.203  12-Sep-2018  msaitoh Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.
 1.202  03-Jul-2018  msaitoh - Print Power Management Control/status register in 32bit.
- Simplify.
 1.201  09-May-2018  msaitoh branches: 1.201.2;
Fix typo. s/TPL/TLP/
 1.200  01-Feb-2018  msaitoh branches: 1.200.2;
- Add PCie Link Activation ECN.
- Use macro.
- KNF.
 1.199  01-Feb-2018  msaitoh Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
because it's not used.
- Remove unsed code.
 1.198  01-Feb-2018  msaitoh "s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.
 1.197  18-Dec-2017  msaitoh Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.

NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
 1.196  25-Oct-2017  msaitoh Whitespace fix.
 1.195  24-Oct-2017  msaitoh Print Error Source Identification register correctly.
 1.194  19-Oct-2017  msaitoh Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.
 1.193  12-Oct-2017  msaitoh IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x
 1.192  10-Oct-2017  msaitoh Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
 1.191  05-Oct-2017  msaitoh - Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.
 1.190  13-Jul-2017  msaitoh - Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.
 1.189  15-Jun-2017  flxd Fix printf format/argument.
 1.188  15-Jun-2017  msaitoh Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.
 1.187  15-Jun-2017  msaitoh For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.
 1.186  08-Jun-2017  msaitoh For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.

Tested with BCM5709:
- Target Link Speed: unknown value (0)
+ Target Link Speed: 2.5GT/s
 1.185  07-Jun-2017  msaitoh Fix to print the following bit fields correctly.
- Supported Link Speeds Vector in LCAP2
- Lower SKP OS Generation Supported Speed Vector in LCAP2
- Lower SKP OS Reception Supported Speed Vector in LCAP2
- Enable Lower SKP OS Generation Vector in LCTL3

Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
- Maximum Link Speed in LCAP
- Current Link Speed in LCSR
- Target Link Speed in LCSR2
 1.184  05-Jun-2017  msaitoh Add missing return to print the Slot Power Limit Value correctly.
 1.183  29-May-2017  msaitoh branches: 1.183.2;
Print MSI Message data in 32bits when the Extended Message Data Capable bit
is set.
 1.182  24-May-2017  msaitoh Decode TPH Requester Control register.
 1.181  22-May-2017  msaitoh - The Captured Slot Power Limit value is only for device which has upsteam
port.
- The following three registers are the same encoding, so use the same
function:
- the Captured Slot Power Limit in the Device Capability register of PICe
capability.
- the Slot Power Limit in Slot Capability register of PCIe capability.
- the Base Power and Data Scale in the Data Register of Power Budgeting
capability.
- Fix the alternative encoding check of power limit as document. Add check if
scale equals to 0.
 1.180  09-May-2017  msaitoh A device except Root Complex integrated has a link, so print link related
registers on device except Root Complex Integrated Endpoint and Root Complex
Event Collector.
 1.179  27-Apr-2017  msaitoh Check slot registers if a device is PCI/PCI-X to PCI Express Bridge. Tested
with Pericom Semiconductors(Diodes) PI7C9X111SL PCIe to PCI Reverse Bridge.
 1.178  21-Apr-2017  kre branches: 1.178.2;

For want of a comma, the compiler was lost.
 1.177  21-Apr-2017  msaitoh Add Flattening Portal Bridge capability ID and Hierarchy ID extended
capability ID.
 1.176  20-Apr-2017  msaitoh Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.
 1.175  20-Apr-2017  msaitoh Add 0x for register output.
 1.174  18-Apr-2017  msaitoh Add missing ':'
 1.173  17-Apr-2017  msaitoh Use macro. No functional change.
 1.172  06-Apr-2017  msaitoh Fix typos:
- s/Readness/Readiness/
- s/Presense/Presence/
- s/supportted/supported/
- s/Rquester/Requester/
- s/Check Enab/Check Enable/
 1.171  30-Mar-2017  msaitoh Fix a bug that SR-IOV's system page size was doubled. ffs()'s bit are
numbered starting from 1.
 1.170  28-Mar-2017  msaitoh Use macro. No functional change.
 1.169  28-Mar-2017  msaitoh Use correct macro "PCI_SATA_REV" instead of PCI_MSIX_CTL for SATA revision
register. This is not a real bug because PCI_SATA_REV and PCI_MSIX_CTL have
the same value.
 1.168  17-Mar-2017  msaitoh Don't print BAR's window size on pcictl pciN dump again
because there is no way to know it's correct value from
userland now.
 1.167  17-Mar-2017  msaitoh - Don't try to sizing a BAR not if a device is host bridge but a device's
PCI_COMMAND_MEM_ENABLE is set.
- Fix 17 years old bug that all effective BARs are marked "not sized" on
pcictl pciN dump.
- Print BAR's window size on pcictl pciN dump.
- remove extra "(?)"
 1.166  14-Mar-2017  msaitoh ECN: Change Root Complex Event Collector Class Code
- Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type in PCIe
extend capability to know whether it's RCEC or IOMMU.
 1.165  14-Mar-2017  msaitoh Pint PCI Interface name if available.
 1.164  14-Mar-2017  msaitoh Add two new PCI classes:
- processing accelerators
- non-essential instrumentation
 1.163  14-Mar-2017  msaitoh No functional change:
- modify variable names
- KNF
 1.162  27-Feb-2017  christos fix printf formats (clang build)
 1.161  27-Feb-2017  msaitoh Decode AGP capability.
 1.160  26-Feb-2017  msaitoh - Fix the base power's value in the power budget capability.
- Fix typo (s/Maximun/Maximum/)
 1.159  24-Feb-2017  msaitoh Use macro. KNF. No functional change.
 1.158  24-Feb-2017  msaitoh Fix 0x%u...
 1.157  15-Feb-2017  msaitoh - Print Data Select and Data Scale in pci_conf_print_pcipm_cap().
- The Message Data register of MSI cap is not 32bit but 16bit.
- When the PCIE_LCAP_MAX_SPEED bitfiled is 0, it means it supports 2.5GT/s only.
- Print link de-emphasis value by "-X dB".
- Print Completion Timeout Ranges Supported filed with alphabets.
- Print TPH Completer Supported fileld's meaning.
- Print PCIE_DCAP2_MAX_EETLP correctly. 0 means 4 End-End TLP Prefixes.
- If the Supported Link Speed Vector is 0, the Link Capability 2 register is not
implemented. Don't decode LCAP2 when the vector is 0.
- The ACS's Egress Control Vector is 32bit, so print with 0x%08x.
- Print SR-IOV's device ID.
- Use __SHIFTOUT() to avoid using magic number.
- Prefix "0x" for hexadecimal value.
 1.156  28-Dec-2016  msaitoh branches: 1.156.2;
The Power Controller Control bit (PCIE_SLCSR_PCC) in the Slot Control & Status
Register is 0 on power on. Print "Power <on|off>" instead of "<on|off>".
 1.155  02-Nov-2016  pgoyette Protect against buffer overflow.
 1.154  31-Oct-2016  martin Stopgap fix for in-kernel compilation (differences between humanize_number(3)
and humanize_number(9)), ok: msaitoh
 1.153  31-Oct-2016  msaitoh Decode Resizable BAR.
 1.152  20-Oct-2016  msaitoh - pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.
 1.151  19-Oct-2016  msaitoh Add VF Resizable BARs ECN.
 1.150  22-Aug-2016  msaitoh Don't follow an incorrect pointer in an extended capability header. Tested
with Super Micro X10SDV-8C-TLN4F bus 255, device 12, function 0 (BIOS 1.1b).
 1.149  17-Aug-2016  msaitoh Add Dynamic Power Allocation (DPA) ECN support.
 1.148  20-Jun-2016  msaitoh branches: 1.148.2;
B260 "Slot Power Limit" ECN. PCIe 3.1 ECN. September 18, 2015.
 1.147  11-May-2016  msaitoh Add Precision Time Management (PTM) ECN.
 1.146  18-Nov-2015  msaitoh - Add the Auto Slot Power Limit Disable bit in Slot Control register and
the Completion Timeout Prefix/Header Log Capable bit in the AER capability
and control register (ECN: Downstream Port Containment (DPC)).
- Add the Poisoned TLP Egress Block bit (ECN: Enhanced DPC).
- Update Link Capabilities 2 register and Link Control 3 register (ECN:
Separate Refclk Independent SSC Architecture (SRIS))
- ECN: Readiness Notifications (RN)
- Add the Retimer Presence Detect Supported bit in the Link Capabilities 2
register and the Retimer Presence Detected bit in the Link Status 2 register
(ECN: Extension Devices)
 1.145  17-Nov-2015  msaitoh - ARI's function group is not bit 32-24 but 22-20.
- Add the Structure Length field in AF capability register.
- Add Enhanced Allocation extended capability ID (ECN: Enhanced Allocation (EA)
for Memory and I/O Resources).
- Add LN System CLS (ECN: Lightweight Notification (LN) Protocol).
- Add ST Upper and Lower bit definitions (ECN: TLP Processiong Hints).
- Add the Global Invalidate bit in the ATS capability register and the PRG
Response PASID Required bit in the Page Request status register (ECN: PASID
Translation)
- Decode ASPM support bit more (ECN: ASPM Optionally)
- Use __BITS()
 1.144  17-Nov-2015  msaitoh No functional change:
- Add comments.
- Remove obsolete comment.
- Move definitions to better location.
- Rename bit definition.
- KNF.
- Indent.
 1.143  16-Nov-2015  msaitoh Define PCIE_XCAP_{VER,TYPE}(x) and use them.
 1.142  13-Nov-2015  msaitoh Fix register offset to print HyperTransport registers correctly.
 1.141  12-Nov-2015  msaitoh - Restore pci_subr.c rev. 1.135's change in pci_conf_print_caplist().
As wrote in the comment, HyperTransport capability appears multiple times.
pci_conf_cap() reruns only the first entry, so it can't be used here.
- Try to decode HyperTransport capability. Currently, the capability type
of each HyperTransport capability is printed and only the MSI Mapping
capability is decoded.
- Style change.
 1.140  30-Oct-2015  msaitoh - Move PCI_INTRSTR_LEN from pcireg.h to pcivar.h.
- In PCI-X cap, print 2nd bus's PCI-X mode, error protection type, Max clock
frequency and Max clock period.
- In SATA cap, print register location correctly.
- In Virtual Channel cap, print reference clock with "ns".
- In Root Complex Link Declaration, print Link Entry number.
 1.139  21-Oct-2015  msaitoh Fix compile error...
 1.138  21-Oct-2015  msaitoh Decode SATA Capability and Multicast Extendeded Capability.
 1.137  03-Oct-2015  joerg Fix format string.
 1.136  02-Oct-2015  msaitoh Fix a bug that the TPH ST Table is wrongly decoded. Found by llvm.
 1.135  02-Oct-2015  msaitoh PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific
 1.134  27-Jul-2015  msaitoh Add NVMe.
 1.133  24-Nov-2014  msaitoh branches: 1.133.2;
Add PCIe CRS Software Visibility bit.
 1.132  23-Oct-2014  msaitoh - Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
 1.131  23-Oct-2014  msaitoh Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
 1.130  23-Oct-2014  msaitoh Fix typo in comment.
 1.129  06-Oct-2014  msaitoh s/genric/generic/
 1.128  06-Oct-2014  msaitoh - Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
 1.127  22-Sep-2014  msaitoh Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
 1.126  21-Sep-2014  christos Merge the 3 copies of devlist2h.awk that deal with 16 bit key and value
pairs to the compressed one that matt wrote.
 1.125  05-Sep-2014  matt Don't use class or typename as a variable name.
 1.124  09-Jun-2014  msaitoh branches: 1.124.2;
Add IOMMU and the Root Complex Event Collector.
 1.123  30-May-2014  msaitoh - Remove some obsoleted comments.
- KNF.
 1.122  30-May-2014  msaitoh - Add PCI-X capability stuff.
- remove extra ':' in pci_conf_print_pcie_cap()
- Add comments.
 1.121  27-May-2014  msaitoh Print "range: not set" if the decode window isn't set.
 1.120  27-May-2014  msaitoh - Add some register definition for MSI and MSI-X
- print MSI-X capability
 1.119  25-May-2014  njoly Do not crash if subclassp == NULL, seen while attaching rstx(4) which
match PCI_CLASS_UNDEFINED class.
 1.118  24-May-2014  msaitoh Print some PCI Capabilities:
- Vendor specific (ID:0x09)
- Debugport (ID:0x0a)
- Subsystem (ID:0x0d)
- PCI Advanced Features (ID:0x13)
 1.117  24-May-2014  msaitoh - Decode the programming interface field in the Class Code register and print
it.
- Print the cache line size in bytes.
- Print the Link Status 2 register itself.
- Some bits were not printed if the bit is 0. Always print them using with
onoff() macro.
- Print more bits.
- KNF.
- Use macro.
- Add comments.
 1.116  24-May-2014  msaitoh - Fix calculation of supported max payload size in PCIe device capability
register.
- Fix for PCIE_SLCSR_DLLSCE flag.
- invert PCIE_SLCSR_PCC
 1.115  23-May-2014  msaitoh No functional change:
- KNF
- Sort in PCI capability ID order.
- Add comments.
 1.114  23-May-2014  msaitoh - Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.
 1.113  23-May-2014  msaitoh PME# clock is not bit 2 but bit 3. Use the macro!
 1.112  15-May-2014  msaitoh Use onoff() macro.
 1.111  13-May-2014  msaitoh Print 32bit I/O region flag and 64bit memory region flag.
 1.110  12-May-2014  msaitoh Print the range of I/O, non-prefechable memory and prefechable memory.
 1.109  12-May-2014  msaitoh Use macro.
 1.108  12-May-2014  msaitoh Fix newline problem which was added in previous commit.
 1.107  09-May-2014  msaitoh Print the CRS Software Visibility Enable bit and the Crosslink Supported bit.
 1.106  05-Aug-2013  msaitoh branches: 1.106.2;
One more Gb/s -> GT/s fix.
 1.105  21-Apr-2013  msaitoh branches: 1.105.4;
- Print PCIe 2.0 or higher capability registers.
- Print Link related registers only if the device is PCI Express Endpoint,
Legacy PCI Express Endpoint or Root Port of PCI Express Root Complex.
- Don't print Root related registers if the device is Root Complex
Integrated Endpoint and print if the device is Root Complex Event Collector.
- Not Gb/s but GT/s.
 1.104  21-Apr-2013  msaitoh - Add some PCIe 2.0 or higher capability register definitions.
- Rename some registers.
- Add comments.
- Indent.
 1.103  21-Apr-2013  msaitoh Delete "PCI_" from PCIX and PICE capability registers.
 1.102  17-Apr-2013  msaitoh Don't check whether PCIe Slot Control Register is all 0 or not.
For example, 82801I PCI Express Port #1 (devid 0x2940) is really
Root Port and it has the Root Control Register and the default
value is 0 (the document say so and really 0 (Tested with my
machine)).
 1.101  17-Apr-2013  msaitoh - Add slot related registers
- Add root port related registers
- Fix the definition of PCI_PCIE_SLCAP_PSN
- Cleanup
 1.100  17-Apr-2013  msaitoh Add PCI_CAP_SUBVENDOR (= 0x0d).
 1.99  16-Apr-2013  msaitoh Decode some PCIe capability register bits.
 1.98  16-Apr-2013  msaitoh Use macro.
 1.97  16-Apr-2013  msaitoh Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded. The bit field is not 0x4e000000 but 0x3e000000.
 1.96  15-Apr-2013  msaitoh Print some PCIE device type.
 1.95  27-Oct-2012  chs split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.
 1.94  20-Oct-2012  matt Add NVM to the pci mass storage subclass
 1.93  23-Sep-2012  chs add an entry for subclass HD audio.
 1.92  24-Apr-2012  drochner branches: 1.92.2;
print correct link speed for PCIexpress Gen2+
(the decoding code needs to be rewritten, sorry for only adding to
the mess)
 1.91  21-Mar-2012  matt Use an unsigned value to hold the pci_class
 1.90  29-Jan-2012  drochner branches: 1.90.2;
extend the pci_aprint_devinfo slightly to cover the cases commonly
used by drivers: a short name for the quiet/naive case and a string
to override the "pcidevs" based name by one provided by the driver,
ride on yesterday's kernel minor version bump
 1.89  26-Jan-2012  drochner put printing of the pci_devinfo into its own function (not inlined
by purpose) - this is a stack hog, and with this change my uTCA amd64
system boots again
a lot of similar code can be eliminated from pci device drivers this way,
but before doing so (and making the new function part of the module API)
I'd like to consider a modification to make it work with drivers which
prefer to print names from other sources (like pciide)
 1.88  17-Aug-2011  dyoung branches: 1.88.2; 1.88.6;
Redefine PCI_MSI_* and PCI_PCIE_* constants in terms of bits(3).

Use named constants and more conventional variable names in
pci_msi_establish() and pci_msi_disestablish(). Fix a couple of bugs:
pci_msi_establish() returned a pointer to the struct intrhand instead of
to the struct msi_hdl as it was intended to, and pci_msi_disestablish()
did not free(9) the msi_hdl.
 1.87  06-Jun-2011  msaitoh Add two new capabilities(PCI_CAP_SATA and PCI_CAP_PCIAF).
 1.86  11-Dec-2010  matt branches: 1.86.6;
Add code to display MSI capabilities.
 1.85  21-Aug-2010  pgoyette Update the various xxx_verbose modules to conform to the module subsystem's
new locking protocol.
 1.84  25-Jul-2010  pgoyette Move setting of pci_verbose_loaded flag into the module's init routine.
This ensures that the flag is set even if the module was manually loaded
by the user rather than just auto-loaded.
 1.83  06-Jun-2010  pgoyette Update pciverbose module to use module_autoload() rather than module_load().
Load the module right before each attempt to use its features, and let the
module subsystem handle unloading.
 1.82  26-May-2010  martin Do not try to unload the pciverbose module if it had never been loaded.
 1.81  25-May-2010  pgoyette Rework the pciverbose module dispatch vectors to avoid renaming the
externally-visible entrypoint name. Also this avoids a potential
need to bump kernel version.

Requested by dyoung@ and mrg@
 1.80  24-May-2010  pgoyette Extract the vendor/product tables and related access routines into a
separate kernel module. Update pci bus attach routine to load the
module (if available) when we're about to start scanning the bus, and
unload the module after the scan is finished.

On architectures which support loading of modules by the boot loader,
the 'pciverbose' module can be loaded and executed without needing to
rebuild the kernel. On all architectures, using 'options PCIVERBOSE'
in the kernel configuration file will create a 'builtin' module which
is functionally equivalent to previous behavior.

XXX Although not nearly as large as the vendor and product tables,
XXX the PCI class and subclass tables might also be offloaded into
XXX the module at a future time.

XXX Cardbus (and possibly other) drivers should also be modified to
XXX load the module before scanning/attaching devices.
 1.79  04-Mar-2010  dyoung branches: 1.79.2;
Extract both instances of the code that prints the PCI Secondary Status
Register into a subroutine. Use terminology similar to that which
PCI System Architecture (4th Edition) uses. For comparison with PCI
reference books, specify flags and fields with __BIT(n) and __BITS(m, n)
instead of hexadecimal constants.
 1.78  13-Jan-2010  drochner branches: 1.78.2;
fix some bitmask in PCI Express capabilities decoding
being here, fix some typos and add a comma for clarity
 1.77  20-Jan-2009  jmcneill Decode and display PCI Power Management registers when available.
 1.76  17-Nov-2008  matt Store pcidevs in a more compact manner. Instead of many string with duplicate
words, store each word individual in a long string and then store offsets
in the string to that word. This reduces the space needed by half.
 1.75  29-Apr-2008  jmcneill branches: 1.75.6; 1.75.8; 1.75.10;
Oh, so that's how you spell Legacy -- thanks spellcheck!
 1.74  10-Apr-2008  cegger branches: 1.74.2; 1.74.4;
use aprint_*_dev and device_xname
 1.73  19-Oct-2007  ad branches: 1.73.16;
machine/{bus,cpu,intr}.h -> sys/{bus,cpu,intr}.h
 1.72  07-Oct-2007  joerg branches: 1.72.2;
Add some basic parsing of the PCI Express capabilities register.
This is enough to help detect the source of interrupt storms at least
for my Thinkpad.
 1.71  16-Nov-2006  christos branches: 1.71.8; 1.71.22; 1.71.24; 1.71.26;
__unused removal on arguments; approved by core.
 1.70  08-Nov-2006  drochner while we are here, also print the interrupt disable bit
in VERBOSE/pcictl
 1.69  17-Oct-2006  dogcow now that we have -Wno-unused-parameter, back out all the tremendously ugly
code to gratuitously access said parameters.
 1.68  13-Oct-2006  christos more __unused
 1.67  13-Oct-2006  dogcow more unused variable fallout.
 1.66  12-Oct-2006  christos - sprinkle __unused on function decls.
- fix a couple of unused bugs
- no more -Wno-unused for i386
 1.65  03-Sep-2006  christos branches: 1.65.2; 1.65.4;
add missing initializers
 1.64  31-May-2006  drochner -add 2 subclasses new in rev. 3.0 of the spec, and fix a pasto in another
-get power management rev printing right
 1.63  11-Dec-2005  christos branches: 1.63.4; 1.63.6; 1.63.8; 1.63.14;
merge ktrace-lwp.
 1.62  30-Oct-2005  simonb Only include <sys/systm.h> if _KERNEL is defined.
 1.61  28-Jun-2005  thorpej branches: 1.61.2; 1.61.4;
Use ANSI function decls and static.
 1.60  27-Feb-2005  perry nuke trailing whitespace
 1.59  02-Aug-2004  mycroft branches: 1.59.4; 1.59.6;
For the PCIVERBOSE case, separate vendors and products into separate tables.
Eliminating redundant pointers in the tables saves nearly 20K (20% of the table
size). In the process, add a pci_findproduct() and make that and
pci_findvendor() return a "const char *".
 1.58  23-Apr-2004  itojun pass string length (= boundary info) to pci_devinfo so that we do not run over
the end of memory region
 1.57  04-Feb-2004  soren Use the right bits for the AGP version.
 1.56  29-Jun-2003  fvdl branches: 1.56.2;
Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.
 1.55  29-Jun-2003  jdolecek fix typo in comment
 1.54  24-Nov-2002  scw Quell an uninitialised variable warning.
 1.53  21-Sep-2002  drochner call the capability list ptr by its name
 1.52  21-Sep-2002  drochner correct caplist head for Cardbus bridges
 1.51  21-Sep-2002  drochner -corrected "MSI" capability
-added some new subclasses and capabilities
-move capability list printing into a separate function and call it
for each header type (not type 0 only)
 1.50  19-May-2002  sommerfeld Fortunately for us, all interrupt controllers are not 8259's
 1.49  03-May-2002  nathanw branches: 1.49.2;
Make pci_conf_print() dump the device-dependent header in userspace, too.
 1.48  22-Mar-2002  drochner iadd subclass codes from the 2.3 spec
 1.47  13-Nov-2001  lukem add RCSID
 1.46  13-Nov-2001  enami Include stdio.h when compiled in userland to pull in declaration of printf etc.
 1.45  13-Sep-2001  thorpej Allow this file to be used in userspace, as well.
 1.44  13-Sep-2001  thorpej ANSI'ify.
 1.43  09-Sep-2001  enami Fix sample code in comment; pci_conf_print() takes three arguments.
 1.42  18-Jan-2001  jdolecek branches: 1.42.2; 1.42.4; 1.42.6;
adapt to pci_knowndevs[] being const, make local constant arrays const
 1.41  21-Nov-2000  soren s/iRDA/IrDA/
 1.40  07-Oct-2000  cgd Update for current PCI device class/subclass and capability codes.
(also, tweak the I2O subclass string to be "standard" -- the removal
of version info didn't extend that far.)
 1.39  02-Oct-2000  ad I2O subclasses currently have nothing to do with the protocol version.
 1.38  02-Sep-2000  cgd don't attempt to size Host Bridge BARs. (it's a good way to die.)
provide a clue about 16-bit vs. 32-bit I/O BARs.
 1.37  03-Aug-2000  nathanw When performing pci_config_dump:
- Display the full value of 64-bit BARs.
- Avoid displaying the upper 32 bits of 64-bit BARs as a separate 32-bit BAR.
 1.36  28-Jun-2000  mrg remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>
 1.35  22-Mar-2000  cgd branches: 1.35.4;
opt_pciverbose.h -> opt_pci.h (it's gonna be used by more things, soon)
 1.34  25-Jan-2000  drochner use BUS_SPACE_MAP_PREFETCHABLE instead BUS_SPACE_MAP_CACHEABLE where the
PCI BAR bit is referred to
 1.33  15-Dec-1999  kleink Report the Capability List support bit of the SR and, if set, print the
the Capability list pointer register as such as well as the capabilities
implemented in the list.
 1.32  27-Sep-1999  cgd branches: 1.32.2; 1.32.8;
add classes/subclasses new in PCI 2.2. Needs a bit of cleanup, but then,
so does everything involving configuration space headers and if i don't
get this out of my source tree i'll go insane.
 1.31  21-Dec-1998  drochner use a symbolic definition for the PCI subsystem ID
 1.30  15-Aug-1998  mycroft Make copyright notices with my name consistent.
 1.29  12-Jul-1998  augustss Add USB support. Supported so far:
* UHCI and OHCI host controllers on PCI
* Hubs
* HID devices withe special drivers for mouse and keyboard
* Printers
 1.28  26-Jun-1998  cgd factor out some common code, and enhance functionality slightly: allow
the BAR-printing function to print a name for the register, factor out
a common register-bits function which can handle the fact that type 2
headers have a different size than is usual, and actually do something
useful with the rest of the bits in the type 2 header.
 1.27  28-May-1998  cgd Clean up slightly, abstract pci_conf_print family's base address register
printing into a function, add a bit more pretty-printing of existing stuff.
Implement pretty-printers for type 1 and type 2 headers. (Right now,
these are just quick stabs based on some on-line bridge docs that I have
handy on my laptop. Mmmm, meetings. I'll check the bits when I get
back within reach of my official docs.)
 1.26  18-May-1998  cgd largely reimplement pci_conf_print():
* print all configuration space registers. Then, where possible,
interpret them. (That is, PRESENT ALL THE DATA, then interpret it --
don't hide data behind interpretation. Also, when interpreting
fields, try to print out the specific value that's being interpreted.)
* handle different header types.
* allow caller to specify a function which can interpret the
device-dependent header and is responsible for pretty-printing it.

It spews (use 'options MSGBUFSIZE=...' 8-), but when you want the data,
you really want _all_ of it.

Still needs some cleanup and additional code (e.g. interepretation
of PCI-PCI (type 1) and PCI-Cardbus (type 2(?)) bridge headers).
 1.25  03-May-1998  thorpej In pci_conf_print(), don't print a mapping register if the size is 0.
 1.24  03-May-1998  thorpej Properly compute the region sizes in pci_conf_print(). Bug pointed out
by Chris Demetriou.
 1.23  20-Apr-1998  drochner Avoid "unused variable" warning without PCIVERBOSE.
From mynhier@cs.utk.edu (PR kern/5328).
 1.22  14-Apr-1998  thorpej Add pci_conf_print(), a function to dump the PCI configuration space, useful
in driver debugging. From Zubin D. Dittia <zubin@clouseau.arl.wustl.edu>,
PR #4249.
 1.21  13-Sep-1997  enami Declare PCIVERBOSE by defopt in files.pci. Include opt_pciverbose.h
in pci_subr.c.
 1.20  19-Mar-1997  cgd branches: 1.20.4;
fix multi-function device support, add new known classes/subclasses,
and clean up class/subclass printing. From brb@brig.com via PR 3359.
 1.19  13-Oct-1996  christos backout kprintf changes
 1.18  10-Oct-1996  christos printf -> kprintf, sprintf -> ksprintf
 1.17  02-Mar-1996  cgd remove some colons to be slightly more friendly to things trying to
parse autoconfiguration output.
 1.16  02-Mar-1996  cgd oops; spaces -> tabs
 1.15  02-Mar-1996  cgd if not PCIVERBOSE, don't say that vendor/product is "unknown," just say
what it is.
 1.14  28-Feb-1996  cgd make PCI bus match/attach and sub-device attachment machine-independent.
 1.13  22-Jan-1996  cgd update PCIVERBOSE code in various ways:
(1) remove the 'UNSUPP' keyword from the device list,
because it can't be reasonably used (becuase different
devices may be supported on different machines, for
good reason).
(2) enhance pci_devinfo so that class/subclass information
is optional (so pci_devinfo can be used by drivers that
match classes of devices, and want to look up the
devices' names easily).
(3) more known vendors and devices.
 1.12  16-Aug-1995  cgd check for null subclass pointer. From Todd Mummert
 1.11  21-Jun-1995  cgd fix reference to incorrect struct (paste-o)
 1.10  18-Jun-1995  cgd define and call "pci_devinfo()", which creates a string from the
vendor & product IDs and class information, which is printed if device
isn't found. Optionally (via "PCIVERBOSE" option) does table lookup
to try to see if it knows what the device really is (informational only...).
 1.9  17-Jun-1995  cgd more appropriate name, as this only has PCI support subroutines.
 1.8  23-May-1995  cgd split single-subdevice lookup & attachment into a subroutine
(pci_attach_subdev()). remove pciattach() function and the pcicd cfdriver
struct, the former because thre are a lot of attachment actions which really
are machine-dependent (perhaps even "most"), and the latter because now that
both pcimatch() and pciattach() are machine-dependent it's bad style to
declare them here and it gains nothing.
 1.7  27-Jan-1995  cgd include files from the correct places.
 1.6  04-Nov-1994  mycroft Make a wrapper match function to check the bus and device numbers, rather
than insisting that every driver do it.
 1.5  03-Nov-1994  mycroft Rename pciprobe() to pcimatch(), and move it to pci_machdep.c.
 1.4  03-Nov-1994  mycroft Always use direct configuration.
 1.3  27-Oct-1994  cgd new RCS ID format.
 1.2  10-Aug-1994  mycroft Update some comments.
 1.1  09-Aug-1994  mycroft branches: 1.1.2;
Add PCI autoconfiguration support.
 1.1.2.1  10-Aug-1994  mycroft update from trunk
 1.20.4.1  16-Sep-1997  thorpej Update marc-pcmcia branch from trunk.
 1.32.8.1  27-Dec-1999  wrstuden Pull up to last week's -current.
 1.32.2.3  11-Feb-2001  bouyer Sync with HEAD.
 1.32.2.2  22-Nov-2000  bouyer Sync with HEAD.
 1.32.2.1  20-Nov-2000  bouyer Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.
 1.35.4.2  25-Oct-2001  he Pull up revisions 1.39-1.40 (requested by ad):
Add Mylex DACC960, CAC-EISA, and I2O block/SCSI drivers.
 1.35.4.1  10-Aug-2000  soda Pull up to netbsd-1-5 branch
Approved by: thorpej

When performing pci_config_dump:
Display the full value of 64-bit BARs.
Avoid displaying the upper 32 bits of 64-bit BARs as a separate 32-bit BAR.
by Nathan J Williams <nathanw@netbsd.org>

Revisions pulled up:
> cvs rdiff -r1.36 -r1.37 syssrc/sys/dev/pci/pci_subr.c
 1.42.6.1  01-Oct-2001  fvdl Catch up with -current.
 1.42.4.4  10-Oct-2002  jdolecek sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work
 1.42.4.3  23-Jun-2002  jdolecek catch up with -current on kqueue branch
 1.42.4.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.42.4.1  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.42.2.6  11-Dec-2002  thorpej Sync with HEAD.
 1.42.2.5  18-Oct-2002  nathanw Catch up to -current.
 1.42.2.4  20-Jun-2002  nathanw Catch up to -current.
 1.42.2.3  01-Apr-2002  nathanw Catch up to -current.
(CVS: It's not just a program. It's an adventure!)
 1.42.2.2  14-Nov-2001  nathanw Catch up to -current.
 1.42.2.1  21-Sep-2001  nathanw Catch up to -current.
 1.49.2.1  30-May-2002  gehenna Catch up with -current.
 1.56.2.5  10-Nov-2005  skrll Sync with HEAD. Here we go again...
 1.56.2.4  04-Mar-2005  skrll Sync with HEAD.

Hi Perry!
 1.56.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.56.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.56.2.1  03-Aug-2004  skrll Sync with HEAD
 1.59.6.1  19-Mar-2005  yamt sync with head. xen and whitespace. xen part is not finished.
 1.59.4.1  29-Apr-2005  kent sync with -current
 1.61.4.1  02-Nov-2005  yamt sync with head.
 1.61.2.3  27-Oct-2007  yamt sync with head.
 1.61.2.2  30-Dec-2006  yamt sync with head.
 1.61.2.1  21-Jun-2006  yamt sync with head.
 1.63.14.1  19-Jun-2006  chap Sync with head.
 1.63.8.2  03-Sep-2006  yamt sync with head.
 1.63.8.1  26-Jun-2006  yamt sync with head.
 1.63.6.1  01-Jun-2006  kardel Sync with head.
 1.63.4.1  09-Sep-2006  rpaulo sync with head
 1.65.4.2  10-Dec-2006  yamt sync with head.
 1.65.4.1  22-Oct-2006  yamt sync with head
 1.65.2.1  18-Nov-2006  ad Sync with head.
 1.71.26.1  14-Oct-2007  yamt sync with head.
 1.71.24.1  06-Nov-2007  matt sync with HEAD
 1.71.22.1  26-Oct-2007  joerg Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.
 1.71.8.2  23-Oct-2007  ad Sync with head.
 1.71.8.1  09-Oct-2007  ad Sync with head.
 1.72.2.1  25-Oct-2007  bouyer Sync with HEAD.
 1.73.16.2  17-Jan-2009  mjf Sync with HEAD.
 1.73.16.1  02-Jun-2008  mjf Sync with HEAD.
 1.74.4.5  09-Oct-2010  yamt sync with head
 1.74.4.4  11-Aug-2010  yamt sync with head.
 1.74.4.3  11-Mar-2010  yamt sync with head
 1.74.4.2  04-May-2009  yamt sync with head.
 1.74.4.1  16-May-2008  yamt sync with head.
 1.74.2.1  18-May-2008  yamt sync with head.
 1.75.10.1  24-Feb-2009  snj branches: 1.75.10.1.4; 1.75.10.1.8;
Pull up following revision(s) (requested by jmcneill in ticket #485):
sys/dev/pci/pci_subr.c: revision 1.77
Decode and display PCI Power Management registers when available.
 1.75.10.1.8.1  07-Jan-2011  matt Add/define some MSI support
 1.75.10.1.4.2  05-Nov-2013  matt Pull in support for pci_aprint_devinfo_fancy
 1.75.10.1.4.1  26-Dec-2011  matt Merge -HEAD changes (except for PCIVERBOSE chagnes).
 1.75.8.2  03-Mar-2009  skrll Sync with HEAD.
 1.75.8.1  19-Jan-2009  skrll Sync with HEAD.
 1.75.6.1  13-Dec-2008  haad Update haad-dm branch to haad-dm-base2.
 1.78.2.3  22-Oct-2010  uebayasi Sync with HEAD (-D20101022).
 1.78.2.2  17-Aug-2010  uebayasi Sync with HEAD.
 1.78.2.1  30-Apr-2010  uebayasi Sync with HEAD.
 1.79.2.4  12-Jun-2011  rmind sync with head
 1.79.2.3  05-Mar-2011  rmind sync with head
 1.79.2.2  03-Jul-2010  rmind sync with head
 1.79.2.1  30-May-2010  rmind sync with head
 1.86.6.1  23-Jun-2011  cherry Catchup with rmind-uvmplock merge.
 1.88.6.3  29-Apr-2012  mrg sync to latest -current.
 1.88.6.2  05-Apr-2012  mrg sync to latest -current.
 1.88.6.1  18-Feb-2012  mrg merge to -current.
 1.88.2.4  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.88.2.3  30-Oct-2012  yamt sync with head
 1.88.2.2  23-May-2012  yamt sync with head.
 1.88.2.1  17-Apr-2012  yamt sync with head
 1.90.2.1  05-Aug-2013  martin Pullup

sys/dev/pci/pcireg.h 1.74-1.82 and 1.84 via patch
sys/dev/pci/pci_subr.c 1.92-1.102, 1.104-1.105 via patch

Add some PCI(e) register and bit definitions in pcireg.h.
Fix the definition of PCI_PCIE_SLCAP_PSN.
Fix a bug that IRQ(MSI) bits in PCIe capability register is incorrectly
decoded.
Print more registers in "pcictl dump".
Fix bug in comment.

Requested by msaitoh in ticket #928
 1.92.2.4  03-Dec-2017  jdolecek update from HEAD
 1.92.2.3  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.92.2.2  23-Jun-2013  tls resync from head
 1.92.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.105.4.2  18-May-2014  rmind sync with head
 1.105.4.1  28-Aug-2013  rmind sync with head
 1.106.2.1  10-Aug-2014  tls Rebase.
 1.124.2.3  09-Dec-2016  snj Pull up following revision(s) (requested by pgoyette in ticket #1296):
sys/dev/pci/pci_subr.c: revision 1.155 via patch
Protect against buffer overflow.
 1.124.2.2  14-Dec-2014  martin branches: 1.124.2.2.4;
Pull up following revision(s) (requested by msaitoh in ticket #325):
sys/dev/pci/pcireg.h: revision 1.100
sys/dev/pci/pci_subr.c: revision 1.133
Add PCIe CRS Software Visibility bit.
 1.124.2.1  12-Dec-2014  martin Pull up following revision(s) (requested by msaitoh in ticket #312):
sys/dev/pci/pci_subr.c: revision 1.130
sys/dev/pci/pci_subr.c: revision 1.131
sys/dev/pci/pci_subr.c: revision 1.132
sys/dev/pci/pcireg.h: revision 1.97
sys/dev/pci/pcireg.h: revision 1.98
sys/dev/pci/pcireg.h: revision 1.99
sys/dev/pci/pci_subr.c: revision 1.127
sys/dev/pci/pci_subr.c: revision 1.128
sys/dev/pci/pci_subr.c: revision 1.129
Always print the Slot implemented bit in the PCIe Capabilities
Register using with onoff().
- Add some PCI subclass and interfaces.
- The interface of PCI_SUBCLASS_BRIDGE_RACEWAY is not decoded yet.
- Fix typo in a message.
- Add comment.
- Modify comment.
s/genric/generic/
Add comment.
Fix typo in comment.
Fix a bug that the specification revision of the Power Management function
was incorrectly printed in the output of capability "list".
The value is also printed in the detail output and it has no bug.
- Cleanup pci_conf_print_caplist. Use table. The reason why it loops twice
is that some capabilities appear multiple times (e.g. HyperTransport cap).
- Print the specification revision of Power Management and AGP not in
the capability list part but in the detail part.
Add some HyperTransport related defines. It's required for the MSI.
 1.124.2.2.4.1  18-Jan-2017  skrll Sync with netbsd-5
 1.133.2.8  28-Aug-2017  skrll Sync with HEAD
 1.133.2.7  05-Feb-2017  skrll Sync with HEAD
 1.133.2.6  05-Dec-2016  skrll Sync with HEAD
 1.133.2.5  05-Oct-2016  skrll Sync with HEAD
 1.133.2.4  09-Jul-2016  skrll Sync with HEAD
 1.133.2.3  29-May-2016  skrll Sync with HEAD
 1.133.2.2  27-Dec-2015  skrll Sync with HEAD (as of 26th Dec)
 1.133.2.1  22-Sep-2015  skrll Sync with HEAD
 1.148.2.4  26-Apr-2017  pgoyette Sync with HEAD
 1.148.2.3  20-Mar-2017  pgoyette Sync with HEAD
 1.148.2.2  07-Jan-2017  pgoyette Sync with HEAD. (Note that most of these changes are simply $NetBSD$
tag issues.)
 1.148.2.1  04-Nov-2016  pgoyette Sync with HEAD
 1.156.2.1  21-Apr-2017  bouyer Sync with HEAD
 1.178.2.2  11-May-2017  pgoyette Sync with HEAD
 1.178.2.1  02-May-2017  pgoyette Sync with HEAD - tag prg-localcount2-base1
 1.183.2.14  29-Jan-2022  martin Pull up the following revisions, requested by msaitoh in ticket #1728:

sys/dev/pci/pci_subr.c 1.232-1.239 via patch
sys/dev/pci/pcireg.h 1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
preset. One of them is known to be the default value.
- Fix typo.
 1.183.2.13  03-Dec-2021  martin Pull up the following revisions, requested by msaitoh in ticket #1714:

sys/dev/pci/pcireg.h 1.148-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.217-1.222, 1.224, 1.227-1.232
via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158
sys/dev/pci/ppb.c 1.74

- Print Bridge Config Retry Enable bit and Retimer Presence Detect
Supported bit.
- Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
- Change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Remove unused shift and mask definitions.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
 1.183.2.12  26-Sep-2019  martin Pull up the following revisions, requested by msaitoh in ticket #1388:

sys/dev/pci/pcireg.h 1.147 via patch
sys/dev/pci/pci_subr.c 1.212, 1.215-1.217 via patch

- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard
Timer Status and Discard Timer SERR# Enable bit in pci_subr.c.
- Print some DPC register values not with %04x but with %08x because
those are 32bit.
- Remove whitespace for consistency.
- Use macro.
- Whitespace fixes.
 1.183.2.11  17-Jul-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1295):

sys/dev/pci/pci_subr.c: revision 1.213
sys/dev/pci/ppb.c: revision 1.69

Identify 16GT/s.
 1.183.2.10  17-Jul-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #1292):

sys/dev/pci/pci_subr.c: revision 1.211
sys/dev/pci/pci_subr.c: revision 1.214

Typo (s/vaule/value/)
Print extend capability from 0x25 to 0x29 correctly.
 1.183.2.9  04-Dec-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1118):

sys/dev/pci/pci_subr.c: revision 1.210
sys/dev/pci/pci_subr.c: revision 1.207
sys/dev/pci/pcireg.h: revision 1.143
sys/dev/pci/pci_subr.c: revision 1.208
sys/dev/pci/pcireg.h: revision 1.144
sys/dev/pci/pci_subr.c: revision 1.209
sys/dev/pci/pcireg.h: revision 1.145
sys/dev/pci/pcireg.h: revision 1.146

Decode PCI Enhanced Allocation.

The register offset of the mask and pending register is depend on the 64bit
address capable bit, so fix the definition of PCI MSI vector mask and pending
register. This problem was not a real bug because PCI_MSI{MASK,PENDING} were
not used from anywhere.

The downstream port of PCIe switch is not a root port, so don't print
root port related register. For example, Intel 63xxESB controller's
downstream port device was printed by pcictl(8) with this bug:
 1.183.2.8  30-Oct-2018  sborrill Pull up the following revisions(s) (requested by msaitoh in ticket #1074):
sys/dev/pci/pci_subr.c: revision 1.204-1.206
sys/dev/pci/pcireg.h: revision 1.141-1.142

Root Complex Event Collector Bus Number Association ECN.
- If capability version is 2 (or greater), decode RCEC Associated Bus Numbers
register.
- Don't print TPH requester's ST Table Size if the ST table location field
is not PCI_TPH_REQ_STTBLLOC_TPHREQ because the size field is only applicable
for PCI_TPH_REQ_STTBLLOC_TPHREQ case.
- Add comment.
 1.183.2.7  23-Sep-2018  martin Pull up following revision(s) (requested by msaitoh in ticket #1028):

sys/dev/pci/pci_subr.c: revision 1.203
sys/dev/pci/pcireg.h: revision 1.140

Add ATS Relaxed Ordering supported bit described in Address Translation
Relaxed Ordering ECN.
 1.183.2.6  26-Jul-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #933):
sys/dev/pci/pci_subr.c: revision 1.202
sys/dev/pci/pcireg.h: revision 1.139
sys/dev/pci/ppbreg.h: revision 1.9
VGA 16 bit decode bit is not bit 3 but bit 4.
--
- Print Power Management Control/status register in 32bit.
- Simplify.
 1.183.2.5  26-Jul-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #930):
sys/dev/pci/pci_subr.c: revision 1.201
sys/dev/pci/pcireg.h: revision 1.138
Fix typo. s/TPL/TLP/
 1.183.2.4  26-Feb-2018  snj Pull up following revision(s) (requested by msaitoh in ticket #576):
sys/dev/pci/pci_subr.c: 1.197-1.200
sys/dev/pci/pcireg.h: 1.136-1.137
sys/dev/pci/ppbreg.h: 1.8
Add VGA 16bit decode bit into the PCI bridge control register. This bit is
defined in PCI-to-PCI Bridge Architecture Specification Revision 1.2. This
bit has meaning if the VGA enable bit or the VGA Palette Snoop Enable bit is
set.
NOTE: sys/arch/x86/pci/pci_ranges.c::mmio_range_extend_by_vga_enable() and/or
some other functions should be modified.
"s/above 300W/greater than 300W/" in pci_conf_print_pcie_power(). From
PCIe Base Spec 3.1a Errata 2017-12-13.
Cleanup:
- Don't pass a capability pointer as a argument of pci_conf_find_cap() and
determine the first pointer in the pci_conf_find_cap() function.
- Don't pass a capability pointer as a argument of pci_conf_find_extcap()
because it's not used.
- Remove unsed code.
- Add PCie Link Activation ECN.
- Use macro.
- KNF.
 1.183.2.3  22-Nov-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #371):
sys/dev/pci/pci_subr.c: revision 1.195
sys/dev/pci/pci_subr.c: revision 1.196
Print Error Source Identification register correctly.
Whitespace fix.
 1.183.2.2  21-Nov-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #362):
sys/dev/pci/pcireg.h: revision 1.133
sys/dev/pci/pcireg.h: revision 1.134
sys/dev/pci/pcireg.h: revision 1.135
sys/dev/pci/pci_subr.c: revision 1.190
sys/dev/pci/pci_subr.c: revision 1.191
sys/dev/pci/pci_subr.c: revision 1.192
sys/dev/pci/pci_subr.c: revision 1.193
sys/dev/pci/pci_subr.c: revision 1.194
sys/dev/pci/pcireg.h: revision 1.132
- Official shortname of LN Requester is LNR, so change PCI_EXTCAP_LN_REQ
to PCI_EXTCAP_LNR
- Use macro.
- Add PCI_MAPREG_ROM_ADDR_MASK macro and PCI_MAPREG_ROM_ADDR() macro.
- print PCI_MAPREG_ROM_ENABLE bit.
- Decode Expansion ROM Validation ECN.
- Add Native PCIe Enclosure Management ECN's extended capability type.
Not decoded yet.
Decode IOMMU capability of PCI secure device capability. From "AMD I/O
Virtualization Technology(IOMMU) Specification (#48882) Revision 3.00".
IOMMU cap dump fixes:
- Print Capability Register's value.
- Indent output correctly.
- s/cahced/cached/
- Print MSI Message number with 0x%02x
Fix a bug that the TPH ST table is decoded even if it's not in the TPH
Requester extended capability structure.
 1.183.2.1  04-Jul-2017  martin Pull up following revision(s) (requested by msaitoh in ticket #80):
sys/dev/pci/pci_subr.c: revision 1.184
sys/dev/pci/pci_subr.c: revision 1.185
sys/dev/pci/pci_subr.c: revision 1.186
sys/dev/pci/pci_subr.c: revision 1.187
sys/dev/pci/pci_subr.c: revision 1.188
sys/dev/pci/pci_subr.c: revision 1.189
sys/dev/pci/pcireg.h: revision 1.131
Add missing return to print the Slot Power Limit Value correctly.
Fix to print the following bit fields correctly.
- Supported Link Speeds Vector in LCAP2
- Lower SKP OS Generation Supported Speed Vector in LCAP2
- Lower SKP OS Reception Supported Speed Vector in LCAP2
- Enable Lower SKP OS Generation Vector in LCTL3
Note that the above bitfields start from 0 and the follwing bitfields start
from 1:
- Maximum Link Speed in LCAP
- Current Link Speed in LCSR
- Target Link Speed in LCSR2
For the Target Link Speed in LCSR2, 0 is allowed for a device which supports
2.5GT/s only (and this check also works for devices which compliant to
versions of the base specification prior to 3.0.
Tested with BCM5709:
- Target Link Speed: unknown value (0)
+ Target Link Speed: 2.5GT/s
For Attention Indicator Control bit and Power Indicator Control bit, it's
allowed to be a read only value 0 if corresponding capability register bit
is 0.
Fix a bug that LTR's latency in L1 PM Substates capability and Latency
Tolerance Reporting capability isn't printed correctly.
Fix printf format/argument.
 1.200.2.6  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.200.2.5  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.200.2.4  20-Oct-2018  pgoyette Sync with head
 1.200.2.3  30-Sep-2018  pgoyette Ssync with HEAD
 1.200.2.2  28-Jul-2018  pgoyette Sync with HEAD
 1.200.2.1  21-May-2018  pgoyette Sync with HEAD
 1.201.2.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.201.2.1  10-Jun-2019  christos Sync with HEAD
 1.215.2.6  29-Jan-2022  martin Pull up the following revisions, requested by msaitoh in ticket #1412:

sys/dev/pci/pci_subr.c 1.232-1.239 via patch
sys/dev/pci/pcireg.h 1.62-1.63

- Decode link control2's Compliance Preset/De-emphasis more.
- Decode Physical Layer 16.0 GT/s extended capability.
- Decode Lane Margining at the Receiver extended capability.
- Print "reserved" instead of "unknown" when printing equalization
preset. One of them is known to be the default value.
- Fix typo.
 1.215.2.5  03-Dec-2021  martin Pull up the following revisions, requested by msaitoh in ticket #1384:

sys/dev/pci/pcireg.h 1.152-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.222, 1.227-1.232 via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158, 1.163
sys/dev/pci/ppb.c 1.74

- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
 1.215.2.4  26-Jul-2020  martin Pull up following revision(s) (requested by jdolecek in ticket #1024):

sys/dev/pci/pci_subr.c: revision 1.224

change pci_conf_print() to allocate memory for the regs dynamically
instead of on-stack
 1.215.2.3  19-Mar-2020  martin Pull up following revision(s) (requested by msaitoh in ticket #782):

sys/dev/pci/pcireg.h: revision 1.150
sys/dev/pci/pcireg.h: revision 1.151
sys/dev/pci/pci_subr.c: revision 1.220
sys/dev/pci/pci_subr.c: revision 1.221
sys/dev/pci/pcireg.h: revision 1.149

- Print Bridge Config Retry Enable bit and Retimer Presence Detect Supported
bit.
- Avoid using magic number.

Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.

Remove unused shift and mask definitions.

Add comment.
 1.215.2.2  21-Jan-2020  martin Pull up the following, requested by msaitoh in ticket #629:

sys/dev/pci/pcireg.h 1.148
sys/dev/pci/pci_subr.c 1.218-1.219

- Fix a bug that the virtual channel extended configuration's
arbitration phase register can't be decoded correctly.
- Fix typo.
 1.215.2.1  26-Sep-2019  martin Pull up following revision(s) (requested by msaitoh in ticket #243):

sys/dev/pci/pci_subr.c: revision 1.216
sys/dev/pci/pci_subr.c: revision 1.217

Whitespace fixes. No functional change.

-

Print some DPC register values not with %04x but with %08x because those
are 32bit.
 1.218.2.2  25-Jan-2020  ad Sync with head.
 1.218.2.1  17-Jan-2020  ad Sync with head.
 1.222.2.1  20-Apr-2020  bouyer Sync with HEAD
 1.224.2.1  03-Apr-2021  thorpej Sync with HEAD.
 1.225.4.1  01-Aug-2021  thorpej Sync with HEAD.

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