Cross Reference: /src/sys/dev/pci/pci

Lines Matching refs:capoff
1183 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff)
1190 	rval = regs[o2i(capoff)];
1194 	rval = regs[o2i(capoff + PCI_AGP_STATUS)];
1211 	rval = regs[o2i(capoff + PCI_AGP_COMMAND)];
1264 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
1268 	caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
1269 	pmcsr = regs[o2i(capoff + PCI_PMCSR)];
1311 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff)
1315 	regs += o2i(capoff);
1406 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff)
1417 	reg = regs[o2i(capoff)];
1446 	reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */
1481 		reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))];
1501 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff)
1510 	val = regs[o2i(capoff + PCI_HT_CMD)];
1514 	lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)];
1515 	hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)];
1556 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff)
1561 	val = regs[o2i(capoff + PCI_HT_CMD)];
1563 	printf("\n  HyperTransport Capability Register at 0x%02x\n", capoff);
1578 		ht_captab[off].printfunc(regs, capoff);
1582 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff)
1586 	caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT;
1593 capoff)
1597 	val = regs[o2i(capoff + PCI_DEBUG_BASER)];
1612 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff)
1616 	reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)];
1624 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff)
1630 	reg = regs[o2i(capoff + PCI_SECURE_CAP)];
1660 	reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
1663 	reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)];
1669 	reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
1681 	reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)];
1703 	reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
1888 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff)
1900 	reg = regs[o2i(capoff)];
1951 	reg = regs[o2i(capoff + PCIE_DCAP)];
1989 	reg = regs[o2i(capoff + PCIE_DCSR)];
2010 	reg = regs[o2i(capoff + PCIE_DCSR)];
2022 		reg = regs[o2i(capoff + PCIE_LCAP)];
2059 		reg = regs[o2i(capoff + PCIE_LCSR)];
2105 		reg = regs[o2i(capoff + PCIE_LCSR)];
2126 capoff + PCIE_SLCAP)];
2145 		reg = regs[o2i(capoff + PCIE_SLCSR)];
2218 		reg = regs[o2i(capoff + PCIE_RCR)];
2234 		reg = regs[o2i(capoff + PCIE_RSR)];
2247 	reg = regs[o2i(capoff + PCIE_DCAP2)];
2342 	reg = regs[o2i(capoff + PCIE_DCSR2)];
2377 		reg = regs[o2i(capoff + PCIE_LCAP2)];
2403 		reg = regs[o2i(capoff + PCIE_LCSR2)];
2474 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff)
2480 	reg = regs[o2i(capoff + PCI_MSIX_CTL)];
2486 	reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
2491 	reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)];
2499 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff)
2505 	reg = regs[o2i(capoff + PCI_SATA_REV)];
2511 	reg = regs[o2i(capoff + PCI_SATA_BAR)];
2525 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff)
2531 	reg = regs[o2i(capoff + PCI_AFCAPR)];
2537 	reg = regs[o2i(capoff + PCI_AFCSR)];
2592 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff)
2599 	reg = regs[o2i(capoff + PCI_EA_CAP1)];
2606 		reg = regs[o2i(capoff + PCI_EA_CAP2)];
2612 		entoff = capoff + 8;
2614 		entoff = capoff + 4;
2779     const pcireg_t *regs, int capoff)
2792 	for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
2821 		for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]);
5126 	int off, capoff, endoff, hdrtype;
5167 		capoff = PCI_CAPLISTPTR_REG;
5174 		capoff = PCI_CAPLISTPTR_REG;
5181 		capoff = PCI_CARDBUS_CAPLISTPTR_REG;
5187 		capoff = -1;
5210 		&& (capoff > 0)) {
5212 		pci_conf_print_caplist(pc, tag, regs, capoff);
5214 		pci_conf_print_caplist(regs, capoff);
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