Lines Matching refs:pb
274 get_io_desc(pciconf_bus_t *pb, bus_size_t size)
278 n = pb->niowin;
279 for (i = n; i > 0 && size > pb->pciiowin[i-1].size; i--)
280 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */
281 return &pb->pciiowin[i];
285 get_mem_desc(pciconf_bus_t *pb, bus_size_t size)
289 n = pb->nmemwin;
290 for (i = n; i > 0 && size > pb->pcimemwin[i-1].size; i--)
291 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */
292 return &pb->pcimemwin[i];
300 probe_bus(pciconf_bus_t *pb)
306 pb->ndevs = 0;
307 pb->niowin = 0;
308 pb->nmemwin = 0;
309 pb->freq_66 = 1;
311 pb->fast_b2b = 0;
313 pb->fast_b2b = 1;
315 pb->prefetch = 1;
316 pb->max_mingnt = 0; /* we are looking for the maximum */
317 pb->min_maxlat = 0x100; /* we are looking for the minimum */
318 pb->bandwidth_used = 0;
320 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs));
329 tag = pci_make_tag(pb->pc, pb->busno, device, 0);
331 print_tag(pb->pc, tag);
333 id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
343 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
346 tag = pci_make_tag(pb->pc, pb->busno, device, function);
347 id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
350 if (pb->ndevs + 1 < MAX_CONF_DEV) {
352 print_tag(pb->pc, tag);
358 confmode = pci_conf_hook(pb->pc, pb->busno,
372 if (pci_do_device_query(pb, tag, device,
375 pb->ndevs++;
383 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb)
385 pb->busno = parent->next_busno;
386 pb->next_busno = pb->busno + 1;
403 pciconf_bus_t *pb;
407 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP);
408 pb->cacheline_size = parent->cacheline_size;
409 pb->parent_bus = parent;
410 alloc_busno(parent, pb);
412 pb->mem_align = 0x100000; /* 1M alignment */
413 pb->pmem_align = 0x100000; /* 1M alignment */
414 pb->io_align = 0x1000; /* 4K alignment */
416 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff);
418 pb->swiz = parent->swiz + dev;
420 memset(&pb->io_res, 0, sizeof(pb->io_res));
421 memset(&pb->mem_res, 0, sizeof(pb->mem_res));
422 memset(&pb->pmem_res, 0, sizeof(pb->pmem_res));
424 pb->pc = parent->pc;
425 pb->io_total = pb->mem_total = pb->pmem_total = 0;
427 pb->io_32bit = 0;
431 pb->io_32bit = 1;
434 pb->pmem_64bit = 0;
439 pb->pmem_64bit = 1;
443 pb->mem_64bit = 0;
445 if (probe_bus(pb)) {
446 printf("Failed to probe bus %d\n", pb->busno);
451 pb->last_busno = pb->next_busno - 1;
452 parent->next_busno = pb->next_busno;
453 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno,
454 pb->last_busno);
457 parent->busno, pb->busno, pb->last_busno);
459 if (pb->io_total > 0) {
465 pb->io_total |= pb->io_align - 1; /* Round up */
466 pi = get_io_desc(parent, pb->io_total);
469 pi->size = pb->io_total;
470 pi->align = pb->io_align; /* 4K min alignment */
471 if (parent->io_align < pb->io_align)
472 parent->io_align = pb->io_align;
475 parent->io_total += pb->io_total;
478 if (pb->mem_total > 0) {
484 pb->mem_total |= pb->mem_align - 1; /* Round up */
485 pm = get_mem_desc(parent, pb->mem_total);
488 pm->size = pb->mem_total;
489 pm->align = pb->mem_align; /* 1M min alignment */
490 if (parent->mem_align < pb->mem_align)
491 parent->mem_align = pb->mem_align;
494 parent->mem_total += pb->mem_total;
497 if (pb->pmem_total > 0) {
502 pb->pmem_total |= pb->pmem_align - 1; /* Round up */
503 pm = get_mem_desc(parent, pb->pmem_total);
506 pm->size = pb->pmem_total;
507 pm->align = pb->pmem_align; /* 1M alignment */
508 if (parent->pmem_align < pb->pmem_align)
509 parent->pmem_align = pb->pmem_align;
512 parent->pmem_total += pb->pmem_total;
515 return pb;
517 kmem_free(pb, sizeof(*pb));
537 pci_bar_is_reserved(pciconf_bus_t *pb, pciconf_dev_t *pd, int br)
555 base = pci_conf_read(pb->pc, tag, br);
556 pci_conf_write(pb->pc, tag, br, 0xffffffff);
557 mask = pci_conf_read(pb->pc, tag, br);
558 pci_conf_write(pb->pc, tag, br, base);
568 base64 = pci_conf_read(pb->pc, tag, br + 4);
569 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
570 mask64 = pci_conf_read(pb->pc, tag, br + 4);
571 pci_conf_write(pb->pc, tag, br + 4, base64);
588 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func,
598 pd = &pb->device[pb->ndevs];
599 pd->pc = pb->pc;
605 classreg = pci_conf_read(pb->pc, tag, PCI_CLASS_REG);
607 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG);
608 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
610 if (pci_get_capability(pb->pc, tag, PCI_CAP_EA, &pd->ea_cap_ptr,
613 print_tag(pb->pc, tag);
622 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd);
624 print_tag(pb->pc, tag);
629 pb->fast_b2b = 0;
632 pb->freq_66 = 0;
640 pd->ppb = query_bus(pb, pd, dev);
648 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM);
650 __SHIFTIN(pb->busno, PCI_BRIDGE_BUS_PRIMARY) |
651 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SECONDARY) |
652 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SUBORDINATE);
653 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg);
655 pb->next_busno++;
661 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
667 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz,
671 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
675 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt)
676 pb->max_mingnt = pd->min_gnt;
678 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat)
679 pb->min_maxlat = pd->max_lat;
681 pb->bandwidth_used += pd->min_gnt * 4000000 /
694 bar = pci_conf_read(pb->pc, tag, br);
695 pci_conf_write(pb->pc, tag, br, 0xffffffff);
696 mask = pci_conf_read(pb->pc, tag, br);
697 pci_conf_write(pb->pc, tag, br, bar);
711 print_tag(pb->pc, tag);
717 if (pb->niowin >= MAX_CONF_IO) {
722 pi = get_io_desc(pb, size);
727 if (pb->io_align < pi->size)
728 pb->io_align = pi->size;
731 print_tag(pb->pc, tag);
735 pb->niowin++;
736 pb->io_total += size;
745 bar64 = pci_conf_read(pb->pc, tag, br + 4);
746 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
747 mask64 = pci_conf_read(pb->pc, tag, br + 4);
748 pci_conf_write(pb->pc, tag, br + 4, bar64);
754 print_tag(pb->pc, tag);
762 print_tag(pb->pc, tag);
771 print_tag(pb->pc, tag);
780 if (pb->nmemwin >= MAX_CONF_MEM) {
785 pm = get_mem_desc(pb, size);
792 print_tag(pb->pc, tag);
796 pb->nmemwin++;
798 pb->pmem_total += size;
799 if (pb->pmem_align < pm->size)
800 pb->pmem_align = pm->size;
802 pb->mem_total += size;
803 if (pb->mem_align < pm->size)
804 pb->mem_align = pm->size;
810 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
811 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe);
812 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
813 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar);
816 if (pb->nmemwin >= MAX_CONF_MEM) {
822 pm = get_mem_desc(pb, size);
829 print_tag(pb->pc, tag);
833 pb->nmemwin++;
835 pb->pmem_total += size;
836 if (pb->pmem_align < pm->size)
837 pb->pmem_align = pm->size;
839 pb->mem_total += size;
840 if (pb->mem_align < pm->size)
841 pb->mem_align = pm->size;
852 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
853 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM,
911 setup_iowins(pciconf_bus_t *pb)
918 for (pi = pb->pciiowin; pi < &pb->pciiowin[pb->niowin]; pi++) {
923 rsvd = pci_bar_is_reserved(pb, pd, pi->reg);
925 if (pb->io_res.arena == NULL) {
932 pi->address = pci_allocate_range(&pb->io_res, pi->size,
951 if (!pb->io_32bit && pi->address > 0xFFFF) {
973 setup_memwins(pciconf_bus_t *pb)
983 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) {
989 rsvd = pci_bar_is_reserved(pb, pd, pm->reg);
992 r = &pb->pmem_res;
993 ok64 = pb->pmem_64bit;
995 r = &pb->mem_res;
996 ok64 = pb->mem_64bit && pd->ppb == NULL;
1014 if (~pm->address == 0 && r == &pb->pmem_res) {
1015 r = &pb->mem_res;
1077 if (!pci_bar_is_reserved(pb, pd, pm->reg)) {
1082 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) {
1136 pciconf_bus_t *pb;
1142 pb = pd->ppb;
1144 if (pb->io_res.arena) {
1145 io_base = pb->io_res.min_addr;
1146 io_limit = pb->io_res.max_addr;
1151 if (pb->io_32bit) {
1157 pb->busno);
1164 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) &
1170 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io);
1171 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh);
1175 if (pb->mem_res.arena) {
1176 bad_range = constrain_bridge_mem_range(&pb->mem_res,
1185 printf("Bus %d bridge MEM range out of range. ", pb->busno);
1194 pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem);
1197 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG);
1200 if (pb->pmem_res.arena) {
1201 bad_range = constrain_bridge_mem_range(&pb->pmem_res,
1211 pb->busno);
1220 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem);
1227 pci_conf_write(pb->pc, pd->tag,
1229 pci_conf_write(pb->pc, pd->tag,
1233 rv = configure_bus(pb);
1235 fini_range_resource(&pb->io_res);
1236 fini_range_resource(&pb->mem_res);
1237 fini_range_resource(&pb->pmem_res);
1243 if (pb->fast_b2b)
1261 configure_bus(pciconf_bus_t *pb)
1266 if (pb->ndevs == 0) {
1268 printf("PCI bus %d - no devices\n", pb->busno);
1271 bus_mhz = pb->freq_66 ? 66 : 33;
1272 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */
1274 if (band < pb->bandwidth_used) {
1276 pb->busno, pb->bandwidth_used);
1279 def_ltim = (band - pb->bandwidth_used) / pb->ndevs;
1280 if (def_ltim > pb->min_maxlat)
1281 def_ltim = pb->min_maxlat;
1287 pb->def_ltim = MIN(def_ltim, 255);
1288 pb->max_ltim = MIN(MAX(max_ltim, def_ltim), 255);
1296 if (setup_iowins(pb) || setup_memwins(pb)) {
1305 for (pd = pb->device; pd < &pb->device[pb->ndevs]; pd++) {
1320 if (pb->fast_b2b)
1331 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim);
1334 ltim = MIN (pb->def_ltim, pb->max_ltim);
1348 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) <<
1360 printf("PCI bus %d configured\n", pb->busno);
1549 pciconf_bus_t *pb;
1552 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP);
1553 pb->busno = firstbus;
1554 pb->next_busno = pb->busno + 1;
1555 pb->last_busno = 255;
1556 pb->cacheline_size = cacheline_size;
1557 pb->parent_bus = NULL;
1558 pb->swiz = 0;
1559 pb->io_32bit = 1;
1560 pb->io_res = rs->resources[PCICONF_RESOURCE_IO];
1562 pb->mem_res = rs->resources[PCICONF_RESOURCE_MEM];
1563 if (pb->mem_res.arena == NULL)
1564 pb->mem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM];
1566 pb->pmem_res = rs->resources[PCICONF_RESOURCE_PREFETCHABLE_MEM];
1567 if (pb->pmem_res.arena == NULL)
1568 pb->pmem_res = rs->resources[PCICONF_RESOURCE_MEM];
1574 pb->mem_64bit = mem_region_ok64(&pb->mem_res);
1575 pb->pmem_64bit = mem_region_ok64(&pb->pmem_res);
1577 pb->pc = pc;
1578 pb->io_total = pb->mem_total = pb->pmem_total = 0;
1580 rv = probe_bus(pb);
1581 pb->last_busno = pb->next_busno - 1;
1583 rv = configure_bus(pb);
1588 kmem_free(pb, sizeof(*pb));