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History log of /src/sys/dev/pci/pciconf.c
RevisionDateAuthorComments
 1.55  25-Sep-2022  thorpej Remove unnecessary include of <sys/malloc.h>.
 1.54  13-Aug-2022  jmcneill pciconf: Skip callbacks for reserved ranges if resource allocation fails.

In the event that a BAR write is ignored, no need to notify the callback
of any changes.
 1.53  30-Aug-2021  jmcneill If an allocation cannot be satisfied by the prefetchable range, retry with
the non-prefetchable range.
 1.52  03-Jan-2021  skrll Misc whitespace
 1.51  29-Dec-2020  skrll Add support for Enhanced Allocations as seen in the Cavium ThunderX based
GIGABYTE MT30-GS2-00

From thorpej@. Thanks!
 1.50  20-Oct-2020  jmcneill branches: 1.50.2;
Instead of trying to prevent pciconf from reconfiguring the firmware's
framebuffer, instead allow MD code to register callbacks. If a resource is
changed, the driver can unmap the old resource and remap the new. Do this
with simplefb so the console doesn't explode when the VGA device is
(potentially) reconfigured at boot.
 1.49  10-Oct-2020  jmcneill Add pciconf_resource_reserve. This allows MD code to mark specific memory
and I/O regions as in use. When pciconf finds a device already configured
to use one of these regions, the device config is left as-is.
 1.48  08-Jul-2020  thorpej Turn off pci_conf_debug -- it was enabled by mistake in previous
commit.
 1.47  07-Jul-2020  thorpej Overhaul the interface to pci_configure_bus():
- Don't expose how PCI bus configuration resource management is implemented.
Provide a new resource provider API:

==> pciconf_resource_init() -- Initialize a PCI configuration resources
container.
==> pciconf_resource_add() -- Add a PCI configuration resource to the
container (I/O, MEM, or prefetchable MEM). Multiple resources of
each type may be added.
==> pciconf_resource_fini() -- Tear down the PCI configurtation resources
container once the bus has been configured.

This is much easier to use than the previous method of providing an
extent map for each kind of resource, and works better for e.g. ACPI
platforms that provide potentially multiple PCI resources in tables
provided by firmware.

- Re-implement PCI configuration resource management using vmem arenas,
rather than extent maps.
 1.46  02-Feb-2020  jmcneill Fix null deref for busses with no IO port resources.
 1.45  20-Jan-2020  skrll don't attempt to extent_alloc_subregion outside the parent extent ranges
 1.44  18-Jan-2020  thorpej Fix several problems with pci_configure_bus():
- Track the 64-bit range capability of prefetchable and non-prefetchable
memory separately. Probe the extent maps provided by the caller to
initialize these values. Without this, we never get 64-bit range
capablity on the root bus, and thus are never able to forward it along
to downstream busses.
- Always prefer allocating space for a 64-bit memory BAR > 4GB. We will
fall back on a 32-bit range if no space above 4GB is available.
- Constrain allocation of 32-bit memory BARs (including expansion ROM BARs)
to be below 4GB, even if the window has a larger range available.
- When allocating non-prefetchable memory space for a PCI-PCI bridge, ensure
it falls below 4GB, since a bridge cannot forward a 64-bit non-prefetchable
range.
- Account for expansion ROMs as non-prefetchable memory rather than
prefetchable memory; expansion ROMs have 32-bit BARs, and if a device
with an expansion ROM is downstream of a brige, a 32-bit prefetchable
range might not be available.

Tested by jmcneill@ on an Arm Neoverse N1 SDP, where the previous
code failed to configure all devices correctly.
 1.43  05-Dec-2019  msaitoh branches: 1.43.2;
KNF. No functional change.
 1.42  01-Oct-2019  chs in many device attach paths, allocate memory with KM_SLEEP instead of KM_NOSLEEP
and remove code to handle failures that can no longer happen.
 1.41  01-Mar-2019  msaitoh - Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.
 1.40  01-Mar-2019  msaitoh KNF. No functional change.
 1.39  01-Mar-2019  msaitoh No functional change:
- u_int* -> uint*
- KNF.
 1.38  29-Jan-2019  msaitoh Fix a bug that PCI bridge's prefetchable memory area's configuration
didn't work correctly in pciconf.c::configure_bridge(). Note that this function
is only for "options PCI_NETBSD_CONFIGURE" machines.
 1.37  05-Sep-2014  matt branches: 1.37.20;
Don't use class or typename as a variable name.
 1.36  20-Oct-2012  matt Enforce alignments for buses.
 1.35  20-Oct-2012  matt If exceeding io/mem windows, show the number that got exceeded.
 1.34  27-Jan-2012  para branches: 1.34.6;
converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged
 1.33  24-Aug-2011  dyoung branches: 1.33.2; 1.33.6;
Add to pci_bus_devorder() an argument that tells the number of slots
available in the devs array. Change the type of the devs array from
char to uint8_t. Treat the return value of pci_bus_devorder() as the
number of slots that it filled.

Don't use the __PCI_BUS_DEVORDER #definition to configure the kernel
but let the linker do it. Make pci_bus_devorder() available on all
architectures by adding a default implementation that will DTRT on
all architectures but hpcmips, the only architecture to #define
__PCI_BUS_DEVORDER. On hpcmips, adapt the implementation to the new
calling convention.

XXX I can compile an hpcmips GENERIC kernel, but I don't have a
XXX hpcmips box to test it on.
 1.32  11-Dec-2010  matt Switch to kmem from malloc.
Don't actually set the PREFETCH64 base/limit registers unless they really are
in use.
 1.31  02-Aug-2009  gavan branches: 1.31.4;
If we're going to complain about exceeding the PCI bandwidth, we may as
well say how much we think we're using.
 1.30  24-May-2007  briggs branches: 1.30.32; 1.30.52; 1.30.56;
The number of max_lat units in 1 sec is 4000000 instead of 40000000 (an
extra 0 snuck into the code).
Found when looking at this with dyoung.
 1.29  27-Feb-2006  gdamore branches: 1.29.24; 1.29.26;
Add PCI_MAPREG_TYPE_ROM and allow it to be used with pci_mapreg_map().
Fix to configure (but do not enable) BARs for expansion ROMs.
Reviewed by briggs@
 1.28  10-Feb-2006  gdamore PCI_NETBSD_CONFIGURE should allocate (but not map) address space expansion
ROMS by default. Full discussion at
http://mail-index.netbsd.org/tech-kern/2005/12/16/0023.html
Closes PR kern/32467
Reviewed by briggs@
 1.27  11-Dec-2005  christos branches: 1.27.2; 1.27.4; 1.27.6;
merge ktrace-lwp.
 1.26  25-Mar-2005  tsutsui branches: 1.26.2;
Allow MD PCI code to specify or disable PCI_COMMAND_PARITY_ENABLE
and PCI_CMMAND_SERR_ENABLE in MI pci_configure_bus(9).
Patch from PR kern/27423 by KIYOHARA Takashi with some changes by me,
approved by Allen Briggs.
 1.25  27-Feb-2005  perry branches: 1.25.2;
nuke trailing whitespace
 1.24  11-Feb-2005  simonb White space nit- don't put a space before/after increment/decrement
operators.
 1.23  17-Mar-2004  scw branches: 1.23.8; 1.23.10;
Use PRIu64 and PRIx64 in place of %llu and %llx format strings for
printing variables of type u_int64_t.
 1.22  02-Dec-2003  briggs Configure PCI-Cardbus bridges, too.
Patch from KIYOHARA Takashi on current-users.
 1.21  31-Mar-2003  augustss branches: 1.21.2;
Add an option to disable fast back-to-back transfers since this
breaks certain hardware combinations.
 1.20  27-Nov-2002  simonb In configure_bus() return early if there are no devices on the bus to
configure.
 1.19  25-Nov-2002  thorpej Avoid some "comparison always false" warnings by only compiling
the code in question if ULONG_MAX > 0xffffffff.
 1.18  08-Nov-2002  simonb Add a prototype for set_busreg(), fix a couple of white space nits.
 1.17  30-Jul-2002  augustss Number PCI busses using a simple pre-order numbering instead of
some strange binary split numbering that doesn't work with multiple
bridges on the same bus, nor with deeply nested bridges.
 1.16  27-Jun-2002  briggs Change a 'continue' to a 'break' in switch configuring 64-bit devices.
Add a little more debugging code.
 1.15  21-Feb-2002  kleink branches: 1.15.8; 1.15.10;
As discussed with Jason Thorpe: while the `cacheline_size\' argument is
a byte-size quantity, the CacheLine Size configuration register specifies
the system cacheline size in units of 32-bit words; per PCI Local Bus
Specification, rev. 2.1, section 6.2.4.
 1.14  28-Nov-2001  thorpej Add a "cacheline_size" argument to pci_configure_bus(). It is used
to set the cacheline size in the BHLC register. This should be the
size of the largest D-cache line on a system.
 1.13  13-Nov-2001  lukem add RCSID
 1.12  09-Nov-2001  thorpej Add a "firstbus" argument to pci_configure_bus(), indicating the
first bus number to use, rather than always assuming that we should
start at bus #0.
 1.11  09-Nov-2001  thorpej In query_bus(), use the parent pciconf_bus_t's PCI chipset tag,
not the new bus's (which is potentially uninitialized when some
calls are made).
 1.10  03-Sep-2001  thorpej branches: 1.10.4;
Bump MAX_CONF_DEV to 32, add some missing newlines in error
messages, and add a TODO item (allocate all metadata dynamically).
 1.9  31-Aug-2001  briggs Fix use of uninitialized variable. Missed by gcc, spotted by enami.
 1.8  30-Aug-2001  briggs Respect __PCI_BUS_DEVORDER.
If all devices can handle 66MHz, then use 66MHz.
Triple the number of configured I/O ranges that we can handle on a bus
(8 was insufficient--originally didn't consider multifunction devices)
Allow one to specify which types of memory to configure, I/O, ROM, or
MEM--for example, one could configure only ROM or only non-ROM.
Ensure that the ROM is disabled if we're not configuring it.
Only set PCI_COMMAND_IO_ENABLE/PCI_COMMAND_MEM_ENABLE if there are valid
memory ranges configured.
 1.7  28-Aug-2001  thorpej Add a TODO item: Do this in 2 passes. One pass that configures the
bus (and optionally maps expansion ROMs), and an optional second
pass to disable expansion ROMs that are mapped. This would allow
MD code to possibly execute the expansion ROMs (possibly in an x86
emulator) to configure a device (e.g. a VGA card, which pretty much
needs to be configured by its ROM).
 1.6  28-Aug-2001  thorpej If MD code doesn't provide pci_conf_hook(), then default to not mapping
the expansion ROMs on cards, since address decoders may be shared between
the ROM and PCI memory space on some cards (i.e. "only map the ROM if you're
going to use it, and then unmap it when you're done" is the intended
usage).
 1.5  14-Jun-2001  thorpej branches: 1.5.2;
It's pretty questionable to printf a PCI tag, but if we're going to
do so, at least make the printf compile across the board.
 1.4  13-Jun-2001  simonb Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
- New pmap and revised trap handler.
- Support on-chip timers, PCI controller, UARTs
- Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
- Add in-kernel PPC floating point emulation
- New in{,4}_cksum that is between 1.5 and 5 times faster than the
old version depending on CPU type.
General changes:
- Kernel support for generic dbsym-style symbols.
 1.3  27-May-2001  thorpej Handle non-contiguous BARs. Needed to be able to configure e.g.
IDE and USB on a PIIX3.
 1.2  12-Feb-2001  briggs branches: 1.2.2;
Deal with a lack of the proper type of memory. For example, if a bridge
only supports 16-bit I/O addresses, do not configure it with addresses
having the upper 16-bits non-zero.
 1.1  09-Feb-2001  briggs branches: 1.1.2;
Add an option (defopt) PCI_NETBSD_CONFIGURE that provides PCI bus
configuration (assignment of bus numbers, BARs, timer values,
interrupt lines, etc.).
The interface must be called from m.d. code prior to probing the bus.
It is meant to be called once for each primary (bus == 0) PCI bus in
the system. It will configure any busses behind PCI-PCI bridges.
Section 9 man page for pci_configure_bus() will come soon.
In the meantime, sample usage is in arch/sandpoint/sandpoint/mainbus.c.
[ Reviewed by thorpej ]
 1.1.2.3  12-Mar-2001  bouyer Sync with HEAD.
 1.1.2.2  11-Feb-2001  bouyer Sync with HEAD.
 1.1.2.1  09-Feb-2001  bouyer file pciconf.c was added on branch thorpej_scsipi on 2001-02-11 19:15:59 +0000
 1.2.2.8  11-Dec-2002  thorpej Sync with HEAD.
 1.2.2.7  11-Nov-2002  nathanw Catch up to -current
 1.2.2.6  01-Aug-2002  nathanw Catch up to -current.
 1.2.2.5  28-Feb-2002  nathanw Catch up to -current.
 1.2.2.4  08-Jan-2002  nathanw Catch up to -current.
 1.2.2.3  14-Nov-2001  nathanw Catch up to -current.
 1.2.2.2  21-Sep-2001  nathanw Catch up to -current.
 1.2.2.1  21-Jun-2001  nathanw Catch up to -current.
 1.5.2.4  06-Sep-2002  jdolecek sync kqueue branch with HEAD
 1.5.2.3  16-Mar-2002  jdolecek Catch up with -current.
 1.5.2.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.5.2.1  13-Sep-2001  thorpej Update the kqueue branch to HEAD.
 1.10.4.1  12-Nov-2001  thorpej Sync the thorpej-mips-cache branch with -current.
 1.15.10.1  27-Jun-2002  lukem Pull up revision 1.16 (requested by briggs in ticket #382):
Change a 'continue' to a 'break' in switch configuring 64-bit devices.
Add a little more debugging code.
 1.15.8.2  29-Aug-2002  gehenna catch up with -current.
 1.15.8.1  15-Jul-2002  gehenna catch up with -current.
 1.21.2.6  01-Apr-2005  skrll Sync with HEAD.
 1.21.2.5  04-Mar-2005  skrll Sync with HEAD.

Hi Perry!
 1.21.2.4  15-Feb-2005  skrll Sync with HEAD.
 1.21.2.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.21.2.2  18-Sep-2004  skrll Sync with HEAD.
 1.21.2.1  03-Aug-2004  skrll Sync with HEAD
 1.23.10.3  26-Mar-2005  yamt sync with head.
 1.23.10.2  19-Mar-2005  yamt sync with head. xen and whitespace. xen part is not finished.
 1.23.10.1  12-Feb-2005  yamt sync with head.
 1.23.8.1  29-Apr-2005  kent sync with -current
 1.25.2.1  27-Mar-2005  tron Pull up revision 1.26 (requested by tsutsui in ticket #67):
Allow MD PCI code to specify or disable PCI_COMMAND_PARITY_ENABLE
and PCI_CMMAND_SERR_ENABLE in MI pci_configure_bus(9).
Patch from PR kern/27423 by KIYOHARA Takashi with some changes by me,
approved by Allen Briggs.
 1.26.2.2  03-Sep-2007  yamt sync with head.
 1.26.2.1  21-Jun-2006  yamt sync with head.
 1.27.6.1  22-Apr-2006  simonb Sync with head.
 1.27.4.1  09-Sep-2006  rpaulo sync with head
 1.27.2.2  01-Mar-2006  yamt sync with head.
 1.27.2.1  18-Feb-2006  yamt sync with head.
 1.29.26.1  11-Jul-2007  mjf Sync with head.
 1.29.24.1  27-May-2007  ad Sync with head.
 1.30.56.1  07-Jan-2011  matt Use kmem. Fix prefetchable setting.
 1.30.52.1  24-Dec-2011  matt Fix problem when alignment of a device is > then the alignment of the bus
bus spaces provided.
 1.30.32.1  19-Aug-2009  yamt sync with head.
 1.31.4.1  05-Mar-2011  rmind sync with head
 1.33.6.1  18-Feb-2012  mrg merge to -current.
 1.33.2.2  30-Oct-2012  yamt sync with head
 1.33.2.1  17-Apr-2012  yamt sync with head
 1.34.6.2  03-Dec-2017  jdolecek update from HEAD
 1.34.6.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.37.20.3  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.37.20.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.37.20.1  10-Jun-2019  christos Sync with HEAD
 1.43.2.2  29-Feb-2020  ad Sync with head.
 1.43.2.1  25-Jan-2020  ad Sync with head.
 1.50.2.1  03-Jan-2021  thorpej Sync w/ HEAD.

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