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Lines Matching refs:sc_atac

103 	sc->sc_wdcdev.sc_atac.atac_dev = self;
234 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
247 				sc->sc_wdcdev.sc_atac.atac_udma_cap =
252 					sc->sc_wdcdev.sc_atac.atac_udma_cap =
256 					sc->sc_wdcdev.sc_atac.atac_udma_cap =
262 			sc->sc_wdcdev.sc_atac.atac_udma_cap =
269 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
272 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
278 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
283 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
285 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
288 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
291 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
292 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
294 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
295 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
301 		sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel;
308 		sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel;
313 		sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel;
323 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
330 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
528 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
532 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
538 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
541 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
542 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
543 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
545 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
546 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
547 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
548 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
553 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;