Lines Matching refs:sc_atac
432 sc->sc_wdcdev.sc_atac.atac_dev = self;
521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
534 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
548 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
568 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
578 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
583 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
587 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
591 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
595 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
599 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
603 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
607 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
611 sc->sc_wdcdev.sc_atac
615 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
619 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
623 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
627 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
631 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
636 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
645 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
650 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
653 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
660 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
675 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
684 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
688 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
690 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
692 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
693 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
695 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
696 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
697 if (sc->sc_wdcdev.sc_atac.atac_set_modes == NULL)
698 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
699 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
701 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
703 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
708 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
747 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
754 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
775 if (device_getprop_bool(sc->sc_wdcdev.sc_atac.atac_dev,
814 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
818 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
874 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
880 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
886 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
930 sc->sc_wdcdev.sc_atac.atac_dev),
988 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
994 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
997 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
998 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
999 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
1001 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1002 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
1003 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
1004 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
1009 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
1040 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1046 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1075 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
1077 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1089 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1097 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1105 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1146 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
1183 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
1208 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1212 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1217 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
1218 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
1220 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
1222 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
1223 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
1225 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
1227 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1228 sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
1233 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
1238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1245 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
1247 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1254 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1258 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1271 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1279 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1287 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1296 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1305 sc->sc_wdcdev.sc_atac.atac_dev,
1313 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
Indexes created Fri Nov 07 05:10:14 GMT 2025