Cross Reference: /src/sys/dev/sdmmc/sdhc.c

Lines Matching defs:HWRITE4
163 hwrite4(struct sdhc_host *hp, bus_size_t o, uint32_t val)
171 #define HWRITE4(hp, reg, val)		hwrite4(hp, reg, val)
178 	do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
184 	do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
354 		HWRITE4(hp, SDHC_MMC_BOOT, 0);
355 		HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN |
357 		HWRITE4(hp, SDHC_WATERMARK_LEVEL,
483 		HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
683 				HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
757 					HWRITE4(hp, i,
763 					HWRITE4(hp, i,
806 		HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
826 		HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
836 		HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
840 		HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
1209 		HWRITE4(hp, SDHC_CLOCK_CTL,
1212 		HWRITE4(hp, SDHC_CLOCK_CTL,
1850 		HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff);
1852 			HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4,
1868 		HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
1876 		HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16));
1877 		HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1880 			HWRITE4(hp, SDHC_MIX_CTRL, mode |
1884 			HWRITE4(hp, SDHC_TRANSFER_MODE, command << 16);
1886 			HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16));
1891 		HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1990 			HWRITE4(hp, SDHC_DMA_ADDR, posaddr);
1992 			HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr);
2124 			HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data));
2213 		HWRITE4(hp, SDHC_DATA, v);
2225 		HWRITE4(hp, SDHC_DATA, v);
2407 			HWRITE4(hp, SDHC_NINTR_STATUS, xstatus);
2531 	HWRITE4(hp, reg, val);
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