Lines Matching refs:SDHC_TRANSFER_COMPLETE
833 SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE;
1680 !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10, false)) {
1924 SDHC_TRANSFER_COMPLETE, SDHC_DMA_TIMEOUT, false)) {
1955 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
1956 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
1960 SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE,
1963 if (status & SDHC_TRANSFER_COMPLETE) {
2039 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
2040 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
2069 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
2167 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
2184 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
2206 while (datalen > 3 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
2219 if (datalen > 0 && !ISSET(status, SDHC_TRANSFER_COMPLETE)) {
2349 if (ISSET(status, SDHC_TRANSFER_COMPLETE))
2390 (xstatus & SDHC_TRANSFER_COMPLETE) &&
2465 SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) {
Indexes created Sat Oct 25 07:10:08 GMT 2025