Lines Matching refs:hp
106 #define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev))
109 hread1(struct sdhc_host *hp, bus_size_t reg)
112 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
113 return bus_space_read_1(hp->iot, hp->ioh, reg);
114 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));
118 hread2(struct sdhc_host *hp, bus_size_t reg)
121 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
122 return bus_space_read_2(hp->iot, hp->ioh, reg);
123 return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2));
126 #define HREAD1(hp, reg) hread1(hp, reg)
127 #define HREAD2(hp, reg) hread2(hp, reg)
128 #define HREAD4(hp, reg) \
129 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
133 hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val)
136 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
137 bus_space_write_1(hp->iot, hp->ioh, o, val);
141 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
143 bus_space_write_4(hp->iot, hp->ioh, o, tmp);
148 hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val)
151 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
152 bus_space_write_2(hp->iot, hp->ioh, o, val);
156 uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
158 bus_space_write_4(hp->iot, hp->ioh, o, tmp);
163 hwrite4(struct sdhc_host *hp, bus_size_t o, uint32_t val)
166 bus_space_write_4(hp->iot, hp->ioh, o, val);
169 #define HWRITE1(hp, reg, val) hwrite1(hp, reg, val)
170 #define HWRITE2(hp, reg, val) hwrite2(hp, reg, val)
171 #define HWRITE4(hp, reg, val) hwrite4(hp, reg, val)
173 #define HCLR1(hp, reg, bits) \
174 do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0)
175 #define HCLR2(hp, reg, bits) \
176 do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0)
177 #define HCLR4(hp, reg, bits) \
178 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
179 #define HSET1(hp, reg, bits) \
180 do if ((bits) != 0) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0)
181 #define HSET2(hp, reg, bits) \
182 do if ((bits) != 0) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0)
183 #define HSET4(hp, reg, bits) \
184 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
255 const struct sdhc_host * const hp = saa->saa_sch;
260 for (size_t host = 0; host < hp->sc->sc_nhosts; host++) {
261 if (hp->sc->sc_host[host] == hp) {
278 struct sdhc_host *hp;
284 hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO);
285 if (hp == NULL) {
290 sc->sc_host[sc->sc_nhosts++] = hp;
293 hp->sc = sc;
294 hp->iot = iot;
295 hp->ioh = ioh;
296 hp->ios = iosize;
297 hp->dmat = sc->sc_dmat;
299 mutex_init(&hp->intr_lock, MUTEX_DEFAULT, IPL_SDMMC);
300 mutex_init(&hp->bus_clock_lock, MUTEX_DEFAULT, IPL_NONE);
301 cv_init(&hp->intr_cv, "sdhcintr");
302 callout_init(&hp->tuning_timer, CALLOUT_MPSAFE);
303 callout_setfunc(&hp->tuning_timer, sdhc_tuning_timer, hp);
305 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
307 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
308 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION);
312 sdhcver = HREAD2(hp, SDHC_HOST_CTL_VERSION);
315 hp->specver = SDHC_SPEC_VERSION(sdhcver);
336 hp->specver = -1;
350 (void)sdhc_host_reset(hp);
352 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
354 HWRITE4(hp, SDHC_MMC_BOOT, 0);
355 HWRITE4(hp, SDHC_HOST_CTL, SDHC_USDHC_BURST_LEN_EN |
357 HWRITE4(hp, SDHC_WATERMARK_LEVEL,
362 HSET4(hp, SDHC_VEND_SPEC,
376 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
378 caps = HREAD4(hp, SDHC_CAPABILITIES);
386 caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES);
387 if (hp->specver >= SDHC_SPEC_VERS_300) {
388 caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2);
399 hp->tuning_timer_count = (caps2 >> SDHC_TIMER_COUNT_SHIFT) &
401 if (hp->tuning_timer_count == 0xf)
402 hp->tuning_timer_count = 0;
403 if (hp->tuning_timer_count)
404 hp->tuning_timer_count =
405 1 << (hp->tuning_timer_count - 1);
416 SET(hp->flags, SHF_USE_DMA);
420 SET(hp->flags, SHF_MODE_DMAEN);
427 if (hp->specver == SDHC_SPEC_VERS_200 &&
429 SET(hp->flags, SHF_USE_ADMA2_64);
432 SET(hp->flags, SHF_USE_ADMA2_32);
438 SET(hp->flags, SHF_MODE_DMAEN);
452 if (hp->specver >= SDHC_SPEC_VERS_300) {
453 hp->clkbase = SDHC_BASE_V3_FREQ_KHZ(caps);
455 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
457 if (hp->clkbase == 0 ||
465 hp->clkbase = sc->sc_clkbase;
467 if (hp->clkbase < 10000 || hp->clkbase > 10000 * 256) {
471 hp->clkbase / 1000);
474 aprint_normal(", %u kHz", hp->clkbase);
480 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
482 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
483 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
494 SET(hp->ocr, MMC_OCR_HCS);
497 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_1_8_V)) {
499 SET(hp->ocr, MMC_OCR_S18A);
503 SET(hp->ocr, MMC_OCR_S18A);
507 SET(hp->ocr, MMC_OCR_S18A);
511 SET(hp->ocr, MMC_OCR_1_65V_1_95V);
516 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
520 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
523 if (hp->specver >= SDHC_SPEC_VERS_300) {
525 if (hp->tuning_timer_count)
526 aprint_normal(" (%us timer)", hp->tuning_timer_count);
535 hp->maxblklen = 512;
539 hp->maxblklen = 1024;
543 hp->maxblklen = 2048;
547 hp->maxblklen = 4096;
554 aprint_normal(", %u byte blocks", hp->maxblklen);
557 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) {
562 PAGE_SIZE, hp->adma_segs, 1, &rseg, BUS_DMA_WAITOK);
568 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg,
569 PAGE_SIZE, (void **)&hp->adma2, BUS_DMA_WAITOK);
576 0, BUS_DMA_WAITOK, &hp->adma_map);
582 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map,
583 hp->adma2, PAGE_SIZE, NULL,
591 memset(hp->adma2, 0, PAGE_SIZE);
595 CLR(hp->flags, SHF_USE_ADMA2_MASK);
605 saa.saa_sch = hp;
606 saa.saa_dmat = hp->dmat;
607 saa.saa_clkmax = hp->clkbase;
609 saa.saa_clkmin = hp->clkbase / 256 / 2046;
611 saa.saa_clkmin = hp->clkbase / 256 / 16;
612 else if (hp->sc->sc_clkmsk != 0)
613 saa.saa_clkmin = hp->clkbase / (hp->sc->sc_clkmsk >>
614 (ffs(hp->sc->sc_clkmsk) - 1));
615 else if (hp->specver >= SDHC_SPEC_VERS_300)
616 saa.saa_clkmin = hp->clkbase / 0x3ff;
618 saa.saa_clkmin = hp->clkbase / 256;
635 if (ISSET(hp->flags, SHF_USE_DMA)) {
637 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
648 hp->sdmmc = config_found(sc->sc_dev, &saa, sdhc_cfprint, CFARGS_NONE);
653 callout_destroy(&hp->tuning_timer);
654 cv_destroy(&hp->intr_cv);
655 mutex_destroy(&hp->bus_clock_lock);
656 mutex_destroy(&hp->intr_lock);
657 free(hp, M_DEVBUF);
666 struct sdhc_host *hp;
670 hp = sc->sc_host[n];
671 if (hp == NULL)
673 if (hp->sdmmc != NULL) {
674 rv = config_detach(hp->sdmmc, flags);
677 hp->sdmmc = NULL;
681 mutex_enter(&hp->intr_lock);
682 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
683 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
685 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
687 sdhc_soft_reset(hp, SDHC_RESET_ALL);
688 mutex_exit(&hp->intr_lock);
690 callout_halt(&hp->tuning_timer, NULL);
691 callout_destroy(&hp->tuning_timer);
692 cv_destroy(&hp->intr_cv);
693 mutex_destroy(&hp->intr_lock);
694 if (hp->ios > 0) {
695 bus_space_unmap(hp->iot, hp->ioh, hp->ios);
696 hp->ios = 0;
698 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) {
699 bus_dmamap_unload(sc->sc_dmat, hp->adma_map);
700 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map);
701 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE);
702 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, 1);
704 free(hp, M_DEVBUF);
715 struct sdhc_host *hp;
723 hp = sc->sc_host[n];
725 for (i = 0; i < sizeof hp->regs; i += 4) {
726 uint32_t v = HREAD4(hp, i);
727 hp->regs[i + 0] = (v >> 0);
728 hp->regs[i + 1] = (v >> 8);
729 if (i + 3 < sizeof hp->regs) {
730 hp->regs[i + 2] = (v >> 16);
731 hp->regs[i + 3] = (v >> 24);
735 for (i = 0; i < sizeof hp->regs; i++) {
736 hp->regs[i] = HREAD1(hp, i);
747 struct sdhc_host *hp;
752 hp = sc->sc_host[n];
753 (void)sdhc_host_reset(hp);
755 for (i = 0; i < sizeof hp->regs; i += 4) {
756 if (i + 3 < sizeof hp->regs) {
757 HWRITE4(hp, i,
758 (hp->regs[i + 0] << 0)
759 | (hp->regs[i + 1] << 8)
760 | (hp->regs[i + 2] << 16)
761 | (hp->regs[i + 3] << 24));
763 HWRITE4(hp, i,
764 (hp->regs[i + 0] << 0)
765 | (hp->regs[i + 1] << 8));
769 for (i = 0; i < sizeof hp->regs; i++) {
770 HWRITE1(hp, i, hp->regs[i]);
781 struct sdhc_host *hp;
785 hp = sc->sc_host[i];
786 (void)sdhc_host_reset(hp);
798 struct sdhc_host *hp = (struct sdhc_host *)sch;
802 KASSERT(mutex_owned(&hp->intr_lock));
805 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
806 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, 0);
808 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
812 hp->vdd = 0;
818 error = sdhc_soft_reset(hp, SDHC_RESET_ALL);
823 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
825 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
826 HWRITE4(hp, SDHC_NINTR_STATUS, SDHC_CMD_TIMEOUT_ERROR << 16);
834 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
836 HWRITE4(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
840 HWRITE4(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
842 HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
843 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK);
845 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
846 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK);
856 struct sdhc_host *hp = (struct sdhc_host *)sch;
859 mutex_enter(&hp->intr_lock);
861 mutex_exit(&hp->intr_lock);
869 struct sdhc_host *hp = (struct sdhc_host *)sch;
871 return hp->ocr;
877 struct sdhc_host *hp = (struct sdhc_host *)sch;
879 return hp->maxblklen;
888 struct sdhc_host *hp = (struct sdhc_host *)sch;
891 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NON_REMOVABLE))
894 if (hp->sc->sc_vendor_card_detect)
895 return (*hp->sc->sc_vendor_card_detect)(hp->sc);
897 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
908 struct sdhc_host *hp = (struct sdhc_host *)sch;
911 if (hp->sc->sc_vendor_write_protect)
912 return (*hp->sc->sc_vendor_write_protect)(hp->sc);
914 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
926 struct sdhc_host *hp = (struct sdhc_host *)sch;
933 mutex_enter(&hp->intr_lock);
938 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_PWR0)) {
939 hp->vdd = 0;
940 HWRITE1(hp, SDHC_POWER_CTL, 0);
945 (void)sdhc_host_reset1(hp);
946 callout_halt(&hp->tuning_timer, &hp->intr_lock);
953 ocr &= hp->ocr;
969 if (vdd == hp->vdd)
972 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
978 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SINGLE_POWER_WRITE)) {
979 HWRITE1(hp, SDHC_POWER_CTL,
982 reg = HREAD1(hp, SDHC_POWER_CTL) & pcmask;
983 HWRITE1(hp, SDHC_POWER_CTL, reg);
986 HWRITE1(hp, SDHC_POWER_CTL, reg);
989 HWRITE1(hp, SDHC_POWER_CTL, reg);
998 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {
1005 hp->vdd = vdd;
1008 mutex_exit(&hp->intr_lock);
1018 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp)
1022 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_CGM)) {
1023 for (div = hp->clkbase / freq; div <= 0x3ff; div++) {
1024 if ((hp->clkbase / div) <= freq) {
1028 //freq = hp->clkbase / div;
1035 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_HAVE_DVS)) {
1036 u_int dvs = (hp->clkbase + freq - 1) / freq;
1045 HDEVNAME(hp), freq, div * 2, dvs + 1));
1046 //freq = hp->clkbase / (div * 2) * (dvs + 1);
1057 if (hp->sc->sc_clkmsk != 0) {
1058 div = howmany(hp->clkbase, freq);
1059 if (div > (hp->sc->sc_clkmsk >> (ffs(hp->sc->sc_clkmsk) - 1)))
1061 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1);
1062 //freq = hp->clkbase / div;
1065 if (hp->specver >= SDHC_SPEC_VERS_300) {
1066 div = howmany(hp->clkbase, freq);
1074 //freq = hp->clkbase / (div ? div * 2 : 1);
1078 if ((hp->clkbase / div) <= freq) {
1080 //freq = hp->clkbase / div;
1098 struct sdhc_host *hp = (struct sdhc_host *)sch;
1106 present = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
1109 if (present && sdhc_card_detect(hp)) {
1110 aprint_normal_dev(hp->sc->sc_dev,
1115 if (hp->sc->sc_vendor_bus_clock) {
1116 mutex_enter(&hp->bus_clock_lock);
1117 error = (*hp->sc->sc_vendor_bus_clock)(hp->sc, freq);
1118 mutex_exit(&hp->bus_clock_lock);
1123 mutex_enter(&hp->intr_lock);
1128 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1129 HCLR4(hp, SDHC_VEND_SPEC,
1135 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1136 HCLR4(hp, SDHC_CLOCK_CTL, 0xfff8);
1138 HSET4(hp, SDHC_CLOCK_CTL, 0x80f0);
1142 HCLR2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
1147 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1149 HSET4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN);
1151 HCLR4(hp, SDHC_MIX_CTRL, SDHC_USDHC_DDR_EN);
1152 } else if (hp->specver >= SDHC_SPEC_VERS_300) {
1153 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK);
1155 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR104);
1158 HSET2(hp, SDHC_HOST_CTL2,
1161 HSET2(hp, SDHC_HOST_CTL2,
1166 HSET2(hp, SDHC_HOST_CTL2,
1169 HSET2(hp, SDHC_HOST_CTL2,
1173 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_SDR12);
1181 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_SLOW_SDR50)) {
1189 if (!sdhc_clock_divisor(hp, freq, &div)) {
1191 aprint_error_dev(hp->sc->sc_dev,
1196 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1205 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_SDSTB))
1209 HWRITE4(hp, SDHC_CLOCK_CTL,
1211 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1212 HWRITE4(hp, SDHC_CLOCK_CTL,
1215 reg = HREAD2(hp, SDHC_CLOCK_CTL);
1217 HWRITE2(hp, SDHC_CLOCK_CTL, reg | div);
1223 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1224 HSET4(hp, SDHC_VEND_SPEC,
1227 } else if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1229 HSET4(hp, SDHC_CLOCK_CTL,
1232 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
1234 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL),
1246 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) {
1247 HSET1(hp, SDHC_SOFTWARE_RESET, SDHC_INIT_ACTIVE);
1255 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET),
1265 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1266 HSET4(hp, SDHC_VEND_SPEC,
1270 HSET4(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
1276 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
1279 !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_HS_BIT))
1280 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
1282 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED);
1285 mutex_exit(&hp->intr_lock);
1287 if (hp->sc->sc_vendor_bus_clock_post) {
1288 mutex_enter(&hp->bus_clock_lock);
1289 error = (*hp->sc->sc_vendor_bus_clock_post)(hp->sc, freq);
1290 mutex_exit(&hp->bus_clock_lock);
1295 mutex_exit(&hp->intr_lock);
1303 struct sdhc_host *hp = (struct sdhc_host *)sch;
1312 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_8BIT_MODE))
1317 HDEVNAME(hp), width));
1321 if (hp->sc->sc_vendor_bus_width) {
1322 const int error = hp->sc->sc_vendor_bus_width(hp->sc, width);
1327 mutex_enter(&hp->intr_lock);
1329 reg = HREAD1(hp, SDHC_HOST_CTL);
1330 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) {
1338 if (hp->specver >= SDHC_SPEC_VERS_300) {
1343 } else if (width == 8 && hp->specver >= SDHC_SPEC_VERS_300) {
1347 HWRITE1(hp, SDHC_HOST_CTL, reg);
1349 mutex_exit(&hp->intr_lock);
1357 struct sdhc_host *hp = (struct sdhc_host *)sch;
1359 if (hp->sc->sc_vendor_rod)
1360 return (*hp->sc->sc_vendor_rod)(hp->sc, on);
1368 struct sdhc_host *hp = (struct sdhc_host *)sch;
1370 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) {
1371 mutex_enter(&hp->intr_lock);
1373 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1374 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
1376 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
1377 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1379 mutex_exit(&hp->intr_lock);
1386 struct sdhc_host *hp = (struct sdhc_host *)sch;
1388 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) {
1389 mutex_enter(&hp->intr_lock);
1390 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
1391 mutex_exit(&hp->intr_lock);
1398 struct sdhc_host *hp = (struct sdhc_host *)sch;
1401 if (hp->specver < SDHC_SPEC_VERS_300)
1404 mutex_enter(&hp->intr_lock);
1407 if (hp->sc->sc_vendor_signal_voltage != NULL) {
1408 error = hp->sc->sc_vendor_signal_voltage(hp->sc,
1413 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC))
1414 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN);
1417 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC))
1418 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN);
1419 if (hp->sc->sc_vendor_signal_voltage != NULL) {
1420 error = hp->sc->sc_vendor_signal_voltage(hp->sc,
1430 mutex_exit(&hp->intr_lock);
1439 sdhc_execute_tuning1(struct sdhc_host *hp, int timing)
1445 KASSERT(mutex_owned(&hp->intr_lock));
1447 hp->tuning_timing = timing;
1454 if (!ISSET(hp->sc->sc_caps2, SDHC_TUNING_SDR50))
1464 hostctl = HREAD1(hp, SDHC_HOST_CTL);
1467 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY);
1468 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY);
1471 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
1474 HCLR2(hp, SDHC_HOST_CTL2, SDHC_SAMPLING_CLOCK_SEL);
1477 HWRITE2(hp, SDHC_HOST_CTL2, SDHC_EXECUTE_TUNING);
1490 error = sdhc_start_command(hp, &cmd);
1494 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY,
1500 } while (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING && --retry);
1503 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_BUFFER_READ_READY);
1504 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_BUFFER_READ_READY);
1506 if (HREAD2(hp, SDHC_HOST_CTL2) & SDHC_EXECUTE_TUNING) {
1507 HCLR2(hp, SDHC_HOST_CTL2,
1509 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
1510 aprint_error_dev(hp->sc->sc_dev,
1515 if ((HREAD2(hp, SDHC_HOST_CTL2) & SDHC_SAMPLING_CLOCK_SEL) == 0) {
1516 HCLR2(hp, SDHC_HOST_CTL2,
1518 sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
1519 aprint_error_dev(hp->sc->sc_dev,
1524 if (hp->tuning_timer_count) {
1525 callout_schedule(&hp->tuning_timer,
1526 hz * hp->tuning_timer_count);
1535 struct sdhc_host *hp = (struct sdhc_host *)sch;
1538 mutex_enter(&hp->intr_lock);
1539 error = sdhc_execute_tuning1(hp, timing);
1540 mutex_exit(&hp->intr_lock);
1547 struct sdhc_host *hp = arg;
1549 atomic_swap_uint(&hp->tuning_timer_pending, 1);
1555 struct sdhc_host *hp = (struct sdhc_host *)sch;
1556 struct sdhc_softc *sc = hp->sc;
1559 sc->sc_vendor_hw_reset(sc, hp);
1563 sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value)
1570 state = HREAD4(hp, SDHC_PRESENT_STATE);
1577 aprint_error_dev(hp->sc->sc_dev,
1589 struct sdhc_host *hp = (struct sdhc_host *)sch;
1593 mutex_enter(&hp->intr_lock);
1595 if (atomic_cas_uint(&hp->tuning_timer_pending, 1, 0) == 1) {
1596 (void)sdhc_execute_tuning1(hp, hp->tuning_timing);
1600 ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED | SDHC_FLAG_USDHC)) {
1602 if (ISSET(hp->flags, SHF_USE_DMA)) {
1603 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, ready);
1604 HCLR2(hp, SDHC_NINTR_STATUS_EN, ready);
1606 HSET2(hp, SDHC_NINTR_SIGNAL_EN, ready);
1607 HSET2(hp, SDHC_NINTR_STATUS_EN, ready);
1611 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_TIMEOUT)) {
1614 HCLR2(hp, SDHC_EINTR_SIGNAL_EN, eintr);
1615 HCLR2(hp, SDHC_EINTR_STATUS_EN, eintr);
1617 HSET2(hp, SDHC_EINTR_SIGNAL_EN, eintr);
1618 HSET2(hp, SDHC_EINTR_STATUS_EN, eintr);
1622 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_STOP_WITH_TC)) {
1630 error = sdhc_start_command(hp, cmd);
1641 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT*3, probing)) {
1654 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE + 0);
1656 cmd->c_resp[1] = HREAD4(hp, SDHC_RESPONSE + 4);
1657 cmd->c_resp[2] = HREAD4(hp, SDHC_RESPONSE + 8);
1658 cmd->c_resp[3] = HREAD4(hp, SDHC_RESPONSE + 12);
1659 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_RSP136_CRC)) {
1670 DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0]));
1677 sdhc_transfer_data(hp, cmd);
1679 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_BUSY_INTR) &&
1680 !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE, hz * 10, false)) {
1682 HDEVNAME(hp)));
1689 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)
1690 && !ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_LED_ON)) {
1692 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
1696 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_NO_AUTO_STOP) &&
1698 (void)sdhc_soft_reset(hp, SDHC_RESET_CMD|SDHC_RESET_DAT);
1700 mutex_exit(&hp->intr_lock);
1702 DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp),
1708 sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
1710 struct sdhc_softc * const sc = hp->sc;
1718 KASSERT(mutex_owned(&hp->intr_lock));
1721 HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data,
1722 cmd->c_datalen, cmd->c_flags, HREAD4(hp, SDHC_NINTR_STATUS)));
1761 ISSET(hp->flags, SHF_MODE_DMAEN)) {
1790 error = sdhc_wait_state(hp, pmask, 0);
1792 (void) sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
1798 HDEVNAME(hp), blksize, blkcount, mode, command));
1800 if (!ISSET(hp
1805 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
1807 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
1811 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK) && cmd->c_data != NULL) {
1823 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) {
1825 hp->adma2;
1831 hp->adma2;
1839 if (ISSET(hp->flags, SHF_USE_ADMA2_32)) {
1840 struct sdhc_adma2_descriptor32 *desc = hp->adma2;
1843 struct sdhc_adma2_descriptor64 *desc = hp->adma2;
1846 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,
1849 const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr;
1850 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff);
1851 if (ISSET(hp->flags, SHF_USE_ADMA2_64)) {
1852 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4,
1856 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1857 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT);
1858 HSET4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT_ADMA2);
1860 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
1861 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2);
1865 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1866 HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT);
1868 HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
1875 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
1876 HWRITE4(hp, SDHC_BLOCK_SIZE, blksize | (blkcount << 16));
1877 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1878 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
1880 HWRITE4(hp, SDHC_MIX_CTRL, mode |
1881 (HREAD4(hp, SDHC_MIX_CTRL) & ~SDHC_TRANSFER_MODE_MASK));
1884 HWRITE4(hp, SDHC_TRANSFER_MODE, command << 16);
1886 HWRITE4(hp, SDHC_TRANSFER_MODE, mode | (command << 16));
1889 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
1890 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
1891 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
1892 HWRITE2(hp, SDHC_TRANSFER_MODE, mode);
1893 HWRITE2(hp, SDHC_COMMAND, command);
1900 sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
1902 struct sdhc_softc *sc = hp->sc;
1905 KASSERT(mutex_owned(&hp->intr_lock));
1907 DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp),
1914 aprint_error_dev(hp->sc->sc_dev,
1921 if (hp->sc->sc_vendor_transfer_data_dma != NULL) {
1922 error = hp->sc->sc_vendor_transfer_data_dma(sc, cmd);
1923 if (error == 0 && !sdhc_wait_intr(hp,
1929 error = sdhc_transfer_data_dma(hp, cmd);
1932 error = sdhc_transfer_data_pio(hp, cmd);
1938 HDEVNAME(hp), cmd->c_error));
1942 sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd)
1952 KASSERT(mutex_owned(&hp->intr_lock));
1953 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_DMA_INTERRUPT);
1954 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_DMA_INTERRUPT);
1955 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
1956 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
1959 status = sdhc_wait_intr(hp,
1972 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) {
1984 posaddr = HREAD4(hp, SDHC_DMA_ADDR);
1990 HWRITE4(hp, SDHC_DMA_ADDR, posaddr);
1992 HWRITE4(hp, SDHC_DMA_ADDR, dm_segs[++seg].ds_addr);
1996 if (ISSET(hp->flags, SHF_USE_ADMA2_MASK)) {
1997 bus_dmamap_sync(hp->sc->sc_dmat, hp->adma_map, 0,
2005 sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd)
2014 KASSERT(mutex_owned(&hp->intr_lock));
2019 if (ISSET(hp->sc->sc_flags,
2028 if (ISSET(hp->sc->sc_flags,
2037 KASSERT(mutex_owned(&hp->intr_lock));
2038 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & imask);
2039 KASSERT(HREAD2(hp, SDHC_NINTR_STATUS_EN) & SDHC_TRANSFER_COMPLETE);
2040 KASSERT(HREAD2(hp, SDHC_NINTR_SIGNAL_EN) & SDHC_TRANSFER_COMPLETE);
2043 if (!ISSET(HREAD4(hp, SDHC_PRESENT_STATE), pmask)) {
2044 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
2045 HSET4(hp, SDHC_NINTR_SIGNAL_EN, imask);
2047 HSET2(hp, SDHC_NINTR_SIGNAL_EN, imask);
2049 if (!sdhc_wait_intr(hp, imask, SDHC_BUFFER_TIMEOUT, false)) {
2055 error = sdhc_wait_state(hp, pmask, pmask);
2061 (*pio_func)(hp, data, len);
2063 HDEVNAME(hp), len, data));
2069 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
2079 sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
2084 *(uint32_t *)data = le32toh(HREAD4(hp, SDHC_DATA));
2089 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA));
2094 *data = HREAD1(hp, SDHC_DATA);
2100 *(uint16_t *)data = le16toh(HREAD2(hp, SDHC_DATA));
2105 *data = HREAD1(hp, SDHC_DATA);
2111 *data = HREAD1(hp, SDHC_DATA);
2119 sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
2124 HWRITE4(hp, SDHC_DATA, htole32(*(uint32_t *)data));
2129 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data));
2134 HWRITE1(hp, SDHC_DATA, *data);
2140 HWRITE2(hp, SDHC_DATA, htole16(*(uint16_t *)data));
2145 HWRITE1(hp, SDHC_DATA, *data);
2151 HWRITE1(hp, SDHC_DATA, *data);
2159 esdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
2161 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
2164 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_READ_SHIFT) & SDHC_WATERMARK_READ_MASK;
2176 v = HREAD4(hp, SDHC_DATA);
2181 status = HREAD2(hp, SDHC_NINTR_STATUS);
2188 v = HREAD4(hp, SDHC_DATA);
2198 esdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, u_int datalen)
2200 uint16_t status = HREAD2(hp, SDHC_NINTR_STATUS);
2203 const size_t watermark = (HREAD4(hp, SDHC_WATERMARK_LEVEL) >> SDHC_WATERMARK_WRITE_SHIFT) & SDHC_WATERMARK_WRITE_MASK;
2213 HWRITE4(hp, SDHC_DATA, v);
2216 status = HREAD2(hp, SDHC_NINTR_STATUS);
2225 HWRITE4(hp, SDHC_DATA, v);
2231 sdhc_soft_reset(struct sdhc_host *hp, int mask)
2235 KASSERT(mutex_owned(&hp->intr_lock));
2237 DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask));
2240 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);
2246 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_WAIT_RESET) &&
2249 if (ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
2265 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
2270 DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp),
2271 HREAD1(hp, SDHC_SOFTWARE_RESET)));
2275 if (ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED)) {
2276 HSET4(hp, SDHC_DMA_CTL, SDHC_DMA_SNOOP);
2283 sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo, bool probing)
2287 KASSERT(mutex_owned(&hp->intr_lock));
2292 status = hp->intr_status & mask;
2294 if (cv_timedwait(&hp->intr_cv, &hp->intr_lock, timo)
2299 status = hp->intr_status & mask;
2301 error = hp->intr_error_status;
2303 DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status,
2306 hp->intr_status &= ~status;
2307 hp->intr_error_status &= ~error;
2311 device_printf(hp->sc->sc_dev,"dma error\n");
2313 device_printf(hp->sc->sc_dev,"adma error\n");
2315 device_printf(hp->sc->sc_dev,"auto_cmd12 error\n");
2317 device_printf(hp->sc->sc_dev,"current limit error\n");
2319 device_printf(hp->sc->sc_dev,"data end bit error\n");
2321 device_printf(hp->sc->sc_dev,"data crc error\n");
2323 device_printf(hp->sc->sc_dev,"data timeout error\n");
2325 device_printf(hp->sc->sc_dev,"cmd index error\n");
2327 device_printf(hp->sc->sc_dev,"cmd end bit error\n");
2329 device_printf(hp->sc->sc_dev,"cmd crc error\n");
2332 device_printf(hp->sc->sc_dev,"cmd timeout error\n");
2335 device_printf(hp->sc->sc_dev,"cmd timeout (expected)\n");
2339 device_printf(hp->sc->sc_dev,"vendor error %#x\n",
2342 device_printf(hp->sc->sc_dev,"no error\n");
2355 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
2356 (void)sdhc_soft_reset(hp, SDHC_RESET_CMD|SDHC_RESET_DAT);
2357 hp->intr_error_status = 0;
2371 struct sdhc_host *hp;
2378 hp = sc->sc_host[host];
2379 if (hp == NULL)
2382 mutex_enter(&hp->intr_lock);
2386 uint32_t xstatus = HREAD4(hp, SDHC_NINTR_STATUS);
2393 status = xstatus = HREAD4(hp,
2407 HWRITE4(hp, SDHC_NINTR_STATUS, xstatus);
2411 status = HREAD2(hp, SDHC_NINTR_STATUS);
2415 HWRITE2(hp, SDHC_NINTR_STATUS, status);
2418 error = HREAD2(hp, SDHC_EINTR_STATUS);
2419 HWRITE2(hp, SDHC_EINTR_STATUS, error);
2423 DPRINTF(2,("%s: interrupt status=%x error=%x\n", HDEVNAME(hp),
2431 uint8_t adma_err = HREAD1(hp, SDHC_ADMA_ERROR_STATUS);
2432 printf("%s: ADMA error, status %02x\n", HDEVNAME(hp),
2440 if (hp->sdmmc != NULL) {
2441 sdmmc_needs_discover(hp->sdmmc);
2445 HCLR4(hp, SDHC_NINTR_STATUS_EN,
2447 HCLR4(hp, SDHC_NINTR_SIGNAL_EN,
2456 atomic_swap_uint(&hp->tuning_timer_pending, 1);
2466 hp->intr_error_status |= error;
2467 hp->intr_status |= status;
2470 HCLR4(hp, SDHC_NINTR_SIGNAL_EN,
2473 cv_broadcast(&hp->intr_cv);
2481 DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp)));
2482 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
2483 sdmmc_card_intr(hp->sdmmc);
2486 mutex_exit(&hp->intr_lock);
2493 sdhc_host_lock(struct sdhc_host *hp)
2495 return &hp->intr_lock;
2499 sdhc_host_read_1(struct sdhc_host *hp, int reg)
2501 return HREAD1(hp, reg);
2505 sdhc_host_read_2(struct sdhc_host *hp, int reg)
2507 return HREAD2(hp, reg);
2511 sdhc_host_read_4(struct sdhc_host *hp, int reg)
2513 return HREAD4(hp, reg);
2517 sdhc_host_write_1(struct sdhc_host *hp, int reg, uint8_t val)
2519 HWRITE1(hp, reg, val);
2523 sdhc_host_write_2(struct sdhc_host *hp, int reg, uint16_t val)
2525 HWRITE2(hp, reg, val);
2529 sdhc_host_write_4(struct sdhc_host *hp, int reg, uint32_t val)
2531 HWRITE4(hp, reg, val);
2536 sdhc_dump_regs(struct sdhc_host *hp)
2540 HREAD4(hp, SDHC_PRESENT_STATE));
2541 if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_ENHANCED))
2543 HREAD1(hp, SDHC_POWER_CTL));
2545 HREAD2(hp, SDHC_NINTR_STATUS));
2547 HREAD2(hp, SDHC_EINTR_STATUS));
2549 HREAD2(hp, SDHC_NINTR_STATUS_EN));
2551 HREAD2(hp, SDHC_EINTR_STATUS_EN));
2553 HREAD2(hp, SDHC_NINTR_SIGNAL_EN));
2555 HREAD2(hp, SDHC_EINTR_SIGNAL_EN));
2557 HREAD4(hp, SDHC_CAPABILITIES));
2559 HREAD4(hp, SDHC_MAX_CAPABILITIES));
Indexes created Sat Oct 11 14:09:46 GMT 2025