Cross Reference: /src/sys/dev/usb/if

Lines Matching defs:axe_cmd
289 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
332 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
334 	err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data);
335 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
371 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
372 	err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval);
373 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
424 	err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
445 	if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) {
480 	axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, mchash);
482 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
505 	if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) {
562 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL);		\
574 	axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
576 	if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0)
578 	axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
667 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
669 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
673 	axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
675 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
684 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
689 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0,
694 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
698 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
703 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
706 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
710 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT,
715 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
720 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
731 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0,
739 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
744 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
752 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
754 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL);
760 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
764 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
777 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
795 	if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG,
810 		if (axe_cmd(sc, AXE_CMD_SROM_READ, 0,
823 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
927 	/* Set these up now for axe_cmd().  */
931 	if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) {
960 		if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) {
1188 		axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1202 		axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1223 		axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr);
1224 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL);
1225 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL);
1226 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL);
1228 		axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr);
1229 		axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2],
1248 		axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1287 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
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