Lines Matching defs:vgpu
1 /* $NetBSD: vgpu.c,v 1.3 2021/12/19 11:06:55 riastradh Exp $ */
37 __KERNEL_RCSID(0, "$NetBSD: vgpu.c,v 1.3 2021/12/19 11:06:55 riastradh Exp $");
43 void populate_pvinfo_page(struct intel_vgpu *vgpu)
46 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
47 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
48 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
49 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
52 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
53 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
54 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
57 vgpu_aperture_gmadr_base(vgpu);
58 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
59 vgpu_aperture_sz(vgpu);
60 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
61 vgpu_hidden_gmadr_base(vgpu);
62 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
63 vgpu_hidden_sz(vgpu);
65 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
67 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
68 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
70 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
72 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
74 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
75 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
89 /* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
90 * with a weight of 4 on a contended host, different vGPU type has
97 /* Fixed vGPU type table */
105 * intel_gvt_init_vgpu_types - initialize vGPU type list
108 * Initialize vGPU type list based on available resource.
117 /* vGPU type name is defined as GVTg_Vx_y which contains
121 * Depend on physical SKU resource, might see vGPU types like
123 * different types of vGPU on same physical GPU depending on
124 * available resource. Each vGPU type will have "avail_instance"
125 * to indicate how many vGPU instance can be created for this
213 * @vgpu: virtual GPU
218 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
220 mutex_lock(&vgpu->vgpu_lock);
221 vgpu->active = true;
222 mutex_unlock(&vgpu->vgpu_lock);
227 * @vgpu: virtual GPU
233 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
235 mutex_lock(&vgpu->vgpu_lock);
237 vgpu->active = false;
239 if (atomic_read(&vgpu->submission.running_workload_num)) {
240 mutex_unlock(&vgpu->vgpu_lock);
241 intel_gvt_wait_vgpu_idle(vgpu);
242 mutex_lock(&vgpu->vgpu_lock);
245 intel_vgpu_stop_schedule(vgpu);
247 mutex_unlock(&vgpu->vgpu_lock);
252 * @vgpu: virtual GPU
259 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
261 intel_gvt_deactivate_vgpu(vgpu);
263 mutex_lock(&vgpu->vgpu_lock);
264 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
265 intel_vgpu_dmabuf_cleanup(vgpu);
266 mutex_unlock(&vgpu->vgpu_lock);
271 * @vgpu: virtual GPU
276 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
278 struct intel_gvt *gvt = vgpu->gvt;
280 mutex_lock(&vgpu->vgpu_lock);
282 WARN(vgpu->active, "vGPU is still active!\n");
284 intel_gvt_debugfs_remove_vgpu(vgpu);
285 intel_vgpu_clean_sched_policy(vgpu);
286 intel_vgpu_clean_submission(vgpu);
287 intel_vgpu_clean_display(vgpu);
288 intel_vgpu_clean_opregion(vgpu);
289 intel_vgpu_reset_ggtt(vgpu, true);
290 intel_vgpu_clean_gtt(vgpu);
291 intel_gvt_hypervisor_detach_vgpu(vgpu);
292 intel_vgpu_free_resource(vgpu);
293 intel_vgpu_clean_mmio(vgpu);
294 intel_vgpu_dmabuf_cleanup(vgpu);
295 mutex_unlock(&vgpu->vgpu_lock);
298 idr_remove(&gvt->vgpu_idr, vgpu->id);
304 vfree(vgpu);
320 struct intel_vgpu *vgpu;
324 vgpu = vzalloc(sizeof(*vgpu));
325 if (!vgpu)
328 vgpu->id = IDLE_VGPU_IDR;
329 vgpu->gvt = gvt;
330 mutex_init(&vgpu->vgpu_lock);
333 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
335 ret = intel_vgpu_init_sched_policy(vgpu);
339 vgpu->active = false;
341 return vgpu;
344 vfree(vgpu);
350 * @vgpu: virtual GPU
355 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
357 mutex_lock(&vgpu->vgpu_lock);
358 intel_vgpu_clean_sched_policy(vgpu);
359 mutex_unlock(&vgpu->vgpu_lock);
361 vfree(vgpu);
367 struct intel_vgpu *vgpu;
374 vgpu = vzalloc(sizeof(*vgpu));
375 if (!vgpu)
379 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
385 vgpu->id = ret;
386 vgpu->handle = param->handle;
387 vgpu->gvt = gvt;
388 vgpu->sched_ctl.weight = param->weight;
389 mutex_init(&vgpu->vgpu_lock);
390 mutex_init(&vgpu->dmabuf_lock);
391 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
392 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
393 idr_init(&vgpu->object_idr);
394 intel_vgpu_init_cfg_space(vgpu, param->primary);
396 ret = intel_vgpu_init_mmio(vgpu);
400 ret = intel_vgpu_alloc_resource(vgpu, param);
404 populate_pvinfo_page(vgpu);
406 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
410 ret = intel_vgpu_init_gtt(vgpu);
414 ret = intel_vgpu_init_opregion(vgpu);
418 ret = intel_vgpu_init_display(vgpu, param->resolution);
422 ret = intel_vgpu_setup_submission(vgpu);
426 ret = intel_vgpu_init_sched_policy(vgpu);
430 intel_gvt_debugfs_add_vgpu(vgpu);
432 ret = intel_gvt_hypervisor_set_opregion(vgpu);
438 ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
442 return vgpu;
445 intel_vgpu_clean_sched_policy(vgpu);
447 intel_vgpu_clean_submission(vgpu);
449 intel_vgpu_clean_display(vgpu);
451 intel_vgpu_clean_opregion(vgpu);
453 intel_vgpu_clean_gtt(vgpu);
455 intel_gvt_hypervisor_detach_vgpu(vgpu);
457 intel_vgpu_free_resource(vgpu);
459 intel_vgpu_clean_mmio(vgpu);
461 idr_remove(&gvt->vgpu_idr, vgpu->id);
463 vfree(vgpu);
470 * @type: type of the vGPU to create
481 struct intel_vgpu *vgpu;
496 vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
497 if (!IS_ERR(vgpu))
502 return vgpu;
507 * @vgpu: virtual GPU
508 * @dmlr: vGPU Device Model Level Reset or GT Reset
512 * device model reset or GT reset. The caller should hold the vgpu lock.
514 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
515 * the whole vGPU to default state as when it is created. This vGPU function
517 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
518 * assign a vGPU to a virtual machine we must isse such reset first.
522 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
533 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
536 struct intel_gvt *gvt = vgpu->gvt;
541 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
542 vgpu->id, dmlr, engine_mask);
544 vgpu->resetting_eng = resetting_eng;
546 intel_vgpu_stop_schedule(vgpu);
549 * scheduler when the reset is triggered by current vgpu.
552 mutex_unlock(&vgpu->vgpu_lock);
553 intel_gvt_wait_vgpu_idle(vgpu);
554 mutex_lock(&vgpu->vgpu_lock);
557 intel_vgpu_reset_submission(vgpu, resetting_eng);
560 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
561 intel_vgpu_invalidate_ppgtt(vgpu);
564 intel_vgpu_reset_gtt(vgpu);
565 intel_vgpu_reset_resource(vgpu);
568 intel_vgpu_reset_mmio(vgpu, dmlr);
569 populate_pvinfo_page(vgpu);
570 intel_vgpu_reset_display(vgpu);
573 intel_vgpu_reset_cfg_space(vgpu);
575 vgpu->failsafe = false;
576 vgpu->pv_notified = false;
580 vgpu->resetting_eng = 0;
581 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
587 * @vgpu: virtual GPU
592 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
594 mutex_lock(&vgpu->vgpu_lock);
595 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
596 mutex_unlock(&vgpu->vgpu_lock);
Indexes created Tue Oct 14 08:09:56 GMT 2025