Lines Matching defs:DPLL
3363 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3446 * Selects the phase for the 10X DPLL clock for the PCIe
3478 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3484 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
4754 * the DPLL semantics change when the LVDS is assigned to that pipe.
4795 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
9961 /* DPLL control1 */
9976 /* DPLL control2 */
9984 /* DPLL Status */
9988 /* DPLL cfg */
Indexes created Sun Oct 19 02:09:48 GMT 2025