Lines Matching defs:rdev
46 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
48 void rs400_gart_adjust_size(struct radeon_device *rdev)
51 switch (rdev->mc.gtt_size/(1024*1024)) {
62 (unsigned)(rdev->mc.gtt_size >> 20));
65 rdev->mc.gtt_size = 32 * 1024 * 1024;
70 void rs400_gart_tlb_flush(struct radeon_device *rdev)
73 unsigned int timeout = rdev->usec_timeout;
86 int rs400_gart_init(struct radeon_device *rdev)
90 if (rdev->gart.ptr) {
95 switch(rdev->mc.gtt_size / (1024 * 1024)) {
108 r = radeon_gart_init(rdev);
111 if (rs400_debugfs_pcie_gart_info_init(rdev))
113 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
114 return radeon_gart_table_ram_alloc(rdev);
117 int rs400_gart_enable(struct radeon_device *rdev)
126 switch(rdev->mc.gtt_size / (1024 * 1024)) {
152 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
159 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
160 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
161 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
171 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
172 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
185 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
196 rs400_gart_tlb_flush(rdev);
198 (unsigned)(rdev->mc.gtt_size >> 20),
199 (unsigned long long)rdev->gart.table_addr);
200 rdev->gart.ready = true;
204 void rs400_gart_disable(struct radeon_device *rdev)
214 void rs400_gart_fini(struct radeon_device *rdev)
216 radeon_gart_fini(rdev);
217 rs400_gart_disable(rdev);
218 radeon_gart_table_ram_free(rdev);
240 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
243 u32 *gtt = rdev->gart.ptr;
247 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
252 for (i = 0; i < rdev->usec_timeout; i++) {
263 static void rs400_gpu_init(struct radeon_device *rdev)
266 r420_pipes_init(rdev);
267 if (rs400_mc_wait_for_idle(rdev)) {
273 static void rs400_mc_init(struct radeon_device *rdev)
277 rs400_gart_adjust_size(rdev);
278 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
280 rdev->mc.vram_is_ddr = true;
281 rdev->mc.vram_width = 128;
282 r100_vram_init_sizes(rdev);
284 radeon_vram_location(rdev, &rdev->mc, base);
285 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
286 radeon_gtt_location(rdev, &rdev->mc);
287 radeon_update_bandwidth_info(rdev);
290 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
295 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
299 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
303 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
307 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
311 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
319 struct radeon_device *rdev = dev->dev_private;
328 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
389 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
392 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
398 static void rs400_mc_program(struct radeon_device *rdev)
403 r100_mc_stop(rdev, &save);
406 if (rs400_mc_wait_for_idle(rdev))
407 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
409 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
410 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
412 r100_mc_resume(rdev, &save);
415 static int rs400_startup(struct radeon_device *rdev)
419 r100_set_common_regs(rdev);
421 rs400_mc_program(rdev);
423 r300_clock_startup(rdev);
425 rs400_gpu_init(rdev);
426 r100_enable_bm(rdev);
429 r = rs400_gart_enable(rdev);
434 r = radeon_wb_init(rdev);
438 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
440 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
445 if (!rdev->irq.installed) {
446 r = radeon_irq_kms_init(rdev);
451 r100_irq_set(rdev);
452 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
454 r = r100_cp_init(rdev, 1024 * 1024);
456 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
460 r = radeon_ib_pool_init(rdev);
462 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
469 int rs400_resume(struct radeon_device *rdev)
474 rs400_gart_disable(rdev);
476 r300_clock_startup(rdev);
478 rs400_mc_program(rdev);
480 if (radeon_asic_reset(rdev)) {
481 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
486 radeon_combios_asic_init(rdev->ddev);
488 r300_clock_startup(rdev);
490 radeon_surface_init(rdev);
492 rdev->accel_working = true;
493 r = rs400_startup(rdev);
495 rdev->accel_working = false;
500 int rs400_suspend(struct radeon_device *rdev)
502 radeon_pm_suspend(rdev);
503 r100_cp_disable(rdev);
504 radeon_wb_disable(rdev);
505 r100_irq_disable(rdev);
506 rs400_gart_disable(rdev);
510 void rs400_fini(struct radeon_device *rdev)
512 radeon_pm_fini(rdev);
513 r100_cp_fini(rdev);
514 radeon_wb_fini(rdev);
515 radeon_ib_pool_fini(rdev);
516 radeon_gem_fini(rdev);
517 rs400_gart_fini(rdev);
518 radeon_irq_kms_fini(rdev);
519 radeon_fence_driver_fini(rdev);
520 radeon_bo_fini(rdev);
521 radeon_atombios_fini(rdev);
522 kfree(rdev->bios);
523 rdev->bios = NULL;
526 int rs400_init(struct radeon_device *rdev)
531 r100_vga_render_disable(rdev);
533 radeon_scratch_init(rdev);
535 radeon_surface_init(rdev);
538 r100_restore_sanity(rdev);
540 if (!radeon_get_bios(rdev)) {
541 if (ASIC_IS_AVIVO(rdev))
544 if (rdev->is_atom_bios) {
545 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
548 r = radeon_combios_init(rdev);
553 if (radeon_asic_reset(rdev)) {
554 dev_warn(rdev->dev,
560 if (radeon_boot_test_post_card(rdev) == false)
564 radeon_get_clock_info(rdev->ddev);
566 rs400_mc_init(rdev);
568 r = radeon_fence_driver_init(rdev);
572 r = radeon_bo_init(rdev);
575 r = rs400_gart_init(rdev);
578 r300_set_reg_safe(rdev);
581 radeon_pm_init(rdev);
583 rdev->accel_working = true;
584 r = rs400_startup(rdev);
587 dev_err(rdev->dev, "Disabling GPU acceleration\n");
588 r100_cp_fini(rdev);
589 radeon_wb_fini(rdev);
590 radeon_ib_pool_fini(rdev);
591 rs400_gart_fini(rdev);
592 radeon_irq_kms_fini(rdev);
593 rdev->accel_working = false;
Indexes created Mon Oct 13 01:09:56 GMT 2025