1 /* $NetBSD: radeon_rs400.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: radeon_rs400.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 33 34 #include <linux/seq_file.h> 35 #include <linux/slab.h> 36 37 #include <drm/drm_debugfs.h> 38 #include <drm/drm_device.h> 39 #include <drm/drm_file.h> 40 41 #include "radeon.h" 42 #include "radeon_asic.h" 43 #include "rs400d.h" 44 45 /* This files gather functions specifics to : rs400,rs480 */ 46 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 47 48 void rs400_gart_adjust_size(struct radeon_device *rdev) 49 { 50 /* Check gart size */ 51 switch (rdev->mc.gtt_size/(1024*1024)) { 52 case 32: 53 case 64: 54 case 128: 55 case 256: 56 case 512: 57 case 1024: 58 case 2048: 59 break; 60 default: 61 DRM_ERROR("Unable to use IGP GART size %uM\n", 62 (unsigned)(rdev->mc.gtt_size >> 20)); 63 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 64 DRM_ERROR("Forcing to 32M GART size\n"); 65 rdev->mc.gtt_size = 32 * 1024 * 1024; 66 return; 67 } 68 } 69 70 void rs400_gart_tlb_flush(struct radeon_device *rdev) 71 { 72 uint32_t tmp; 73 unsigned int timeout = rdev->usec_timeout; 74 75 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 76 do { 77 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 78 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 79 break; 80 udelay(1); 81 timeout--; 82 } while (timeout > 0); 83 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 84 } 85 86 int rs400_gart_init(struct radeon_device *rdev) 87 { 88 int r; 89 90 if (rdev->gart.ptr) { 91 WARN(1, "RS400 GART already initialized\n"); 92 return 0; 93 } 94 /* Check gart size */ 95 switch(rdev->mc.gtt_size / (1024 * 1024)) { 96 case 32: 97 case 64: 98 case 128: 99 case 256: 100 case 512: 101 case 1024: 102 case 2048: 103 break; 104 default: 105 return -EINVAL; 106 } 107 /* Initialize common gart structure */ 108 r = radeon_gart_init(rdev); 109 if (r) 110 return r; 111 if (rs400_debugfs_pcie_gart_info_init(rdev)) 112 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 113 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 114 return radeon_gart_table_ram_alloc(rdev); 115 } 116 117 int rs400_gart_enable(struct radeon_device *rdev) 118 { 119 uint32_t size_reg; 120 uint32_t tmp; 121 122 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 123 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 124 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 125 /* Check gart size */ 126 switch(rdev->mc.gtt_size / (1024 * 1024)) { 127 case 32: 128 size_reg = RS480_VA_SIZE_32MB; 129 break; 130 case 64: 131 size_reg = RS480_VA_SIZE_64MB; 132 break; 133 case 128: 134 size_reg = RS480_VA_SIZE_128MB; 135 break; 136 case 256: 137 size_reg = RS480_VA_SIZE_256MB; 138 break; 139 case 512: 140 size_reg = RS480_VA_SIZE_512MB; 141 break; 142 case 1024: 143 size_reg = RS480_VA_SIZE_1GB; 144 break; 145 case 2048: 146 size_reg = RS480_VA_SIZE_2GB; 147 break; 148 default: 149 return -EINVAL; 150 } 151 /* It should be fine to program it to max value */ 152 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 153 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 154 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 155 } else { 156 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 157 WREG32(RS480_AGP_BASE_2, 0); 158 } 159 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 160 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 161 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 162 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 163 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 164 WREG32(RADEON_BUS_CNTL, tmp); 165 } else { 166 WREG32(RADEON_MC_AGP_LOCATION, tmp); 167 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 168 WREG32(RADEON_BUS_CNTL, tmp); 169 } 170 /* Table should be in 32bits address space so ignore bits above. */ 171 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 172 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 173 174 WREG32_MC(RS480_GART_BASE, tmp); 175 /* TODO: more tweaking here */ 176 WREG32_MC(RS480_GART_FEATURE_ID, 177 (RS480_TLB_ENABLE | 178 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 179 /* Disable snooping */ 180 WREG32_MC(RS480_AGP_MODE_CNTL, 181 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 182 /* Disable AGP mode */ 183 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 184 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 185 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 186 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 187 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 188 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 189 } else { 190 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 191 tmp |= RS480_GART_INDEX_REG_EN; 192 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 193 } 194 /* Enable gart */ 195 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 196 rs400_gart_tlb_flush(rdev); 197 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 198 (unsigned)(rdev->mc.gtt_size >> 20), 199 (unsigned long long)rdev->gart.table_addr); 200 rdev->gart.ready = true; 201 return 0; 202 } 203 204 void rs400_gart_disable(struct radeon_device *rdev) 205 { 206 uint32_t tmp; 207 208 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 209 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 210 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 211 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 212 } 213 214 void rs400_gart_fini(struct radeon_device *rdev) 215 { 216 radeon_gart_fini(rdev); 217 rs400_gart_disable(rdev); 218 radeon_gart_table_ram_free(rdev); 219 } 220 221 #define RS400_PTE_UNSNOOPED (1 << 0) 222 #define RS400_PTE_WRITEABLE (1 << 2) 223 #define RS400_PTE_READABLE (1 << 3) 224 225 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags) 226 { 227 uint32_t entry; 228 229 entry = (lower_32_bits(addr) & PAGE_MASK) | 230 ((upper_32_bits(addr) & 0xff) << 4); 231 if (flags & RADEON_GART_PAGE_READ) 232 entry |= RS400_PTE_READABLE; 233 if (flags & RADEON_GART_PAGE_WRITE) 234 entry |= RS400_PTE_WRITEABLE; 235 if (!(flags & RADEON_GART_PAGE_SNOOP)) 236 entry |= RS400_PTE_UNSNOOPED; 237 return entry; 238 } 239 240 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 241 uint64_t entry) 242 { 243 u32 *gtt = rdev->gart.ptr; 244 gtt[i] = cpu_to_le32(lower_32_bits(entry)); 245 } 246 247 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 248 { 249 unsigned i; 250 uint32_t tmp; 251 252 for (i = 0; i < rdev->usec_timeout; i++) { 253 /* read MC_STATUS */ 254 tmp = RREG32(RADEON_MC_STATUS); 255 if (tmp & RADEON_MC_IDLE) { 256 return 0; 257 } 258 udelay(1); 259 } 260 return -1; 261 } 262 263 static void rs400_gpu_init(struct radeon_device *rdev) 264 { 265 /* FIXME: is this correct ? */ 266 r420_pipes_init(rdev); 267 if (rs400_mc_wait_for_idle(rdev)) { 268 pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n", 269 RREG32(RADEON_MC_STATUS)); 270 } 271 } 272 273 static void rs400_mc_init(struct radeon_device *rdev) 274 { 275 u64 base; 276 277 rs400_gart_adjust_size(rdev); 278 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 279 /* DDR for all card after R300 & IGP */ 280 rdev->mc.vram_is_ddr = true; 281 rdev->mc.vram_width = 128; 282 r100_vram_init_sizes(rdev); 283 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 284 radeon_vram_location(rdev, &rdev->mc, base); 285 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 286 radeon_gtt_location(rdev, &rdev->mc); 287 radeon_update_bandwidth_info(rdev); 288 } 289 290 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 291 { 292 unsigned long flags; 293 uint32_t r; 294 295 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 296 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 297 r = RREG32(RS480_NB_MC_DATA); 298 WREG32(RS480_NB_MC_INDEX, 0xff); 299 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 300 return r; 301 } 302 303 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 304 { 305 unsigned long flags; 306 307 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 308 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 309 WREG32(RS480_NB_MC_DATA, (v)); 310 WREG32(RS480_NB_MC_INDEX, 0xff); 311 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 312 } 313 314 #if defined(CONFIG_DEBUG_FS) 315 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 316 { 317 struct drm_info_node *node = (struct drm_info_node *) m->private; 318 struct drm_device *dev = node->minor->dev; 319 struct radeon_device *rdev = dev->dev_private; 320 uint32_t tmp; 321 322 tmp = RREG32(RADEON_HOST_PATH_CNTL); 323 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 324 tmp = RREG32(RADEON_BUS_CNTL); 325 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 326 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 327 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 328 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 329 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 330 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 331 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 332 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 333 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 334 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 335 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 336 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 337 tmp = RREG32(RS690_HDP_FB_LOCATION); 338 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 339 } else { 340 tmp = RREG32(RADEON_AGP_BASE); 341 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 342 tmp = RREG32(RS480_AGP_BASE_2); 343 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 344 tmp = RREG32(RADEON_MC_AGP_LOCATION); 345 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 346 } 347 tmp = RREG32_MC(RS480_GART_BASE); 348 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 349 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 350 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 351 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 352 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 353 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 354 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x5F); 356 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 357 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 358 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 359 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 360 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 361 tmp = RREG32_MC(0x3B); 362 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 363 tmp = RREG32_MC(0x3C); 364 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 365 tmp = RREG32_MC(0x30); 366 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 367 tmp = RREG32_MC(0x31); 368 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 369 tmp = RREG32_MC(0x32); 370 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 371 tmp = RREG32_MC(0x33); 372 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 373 tmp = RREG32_MC(0x34); 374 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 375 tmp = RREG32_MC(0x35); 376 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 377 tmp = RREG32_MC(0x36); 378 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 379 tmp = RREG32_MC(0x37); 380 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 381 return 0; 382 } 383 384 static struct drm_info_list rs400_gart_info_list[] = { 385 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 386 }; 387 #endif 388 389 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 390 { 391 #if defined(CONFIG_DEBUG_FS) 392 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 393 #else 394 return 0; 395 #endif 396 } 397 398 static void rs400_mc_program(struct radeon_device *rdev) 399 { 400 struct r100_mc_save save; 401 402 /* Stops all mc clients */ 403 r100_mc_stop(rdev, &save); 404 405 /* Wait for mc idle */ 406 if (rs400_mc_wait_for_idle(rdev)) 407 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 408 WREG32(R_000148_MC_FB_LOCATION, 409 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 410 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 411 412 r100_mc_resume(rdev, &save); 413 } 414 415 static int rs400_startup(struct radeon_device *rdev) 416 { 417 int r; 418 419 r100_set_common_regs(rdev); 420 421 rs400_mc_program(rdev); 422 /* Resume clock */ 423 r300_clock_startup(rdev); 424 /* Initialize GPU configuration (# pipes, ...) */ 425 rs400_gpu_init(rdev); 426 r100_enable_bm(rdev); 427 /* Initialize GART (initialize after TTM so we can allocate 428 * memory through TTM but finalize after TTM) */ 429 r = rs400_gart_enable(rdev); 430 if (r) 431 return r; 432 433 /* allocate wb buffer */ 434 r = radeon_wb_init(rdev); 435 if (r) 436 return r; 437 438 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 439 if (r) { 440 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 441 return r; 442 } 443 444 /* Enable IRQ */ 445 if (!rdev->irq.installed) { 446 r = radeon_irq_kms_init(rdev); 447 if (r) 448 return r; 449 } 450 451 r100_irq_set(rdev); 452 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 453 /* 1M ring buffer */ 454 r = r100_cp_init(rdev, 1024 * 1024); 455 if (r) { 456 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 457 return r; 458 } 459 460 r = radeon_ib_pool_init(rdev); 461 if (r) { 462 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 463 return r; 464 } 465 466 return 0; 467 } 468 469 int rs400_resume(struct radeon_device *rdev) 470 { 471 int r; 472 473 /* Make sur GART are not working */ 474 rs400_gart_disable(rdev); 475 /* Resume clock before doing reset */ 476 r300_clock_startup(rdev); 477 /* setup MC before calling post tables */ 478 rs400_mc_program(rdev); 479 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 480 if (radeon_asic_reset(rdev)) { 481 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 482 RREG32(R_000E40_RBBM_STATUS), 483 RREG32(R_0007C0_CP_STAT)); 484 } 485 /* post */ 486 radeon_combios_asic_init(rdev->ddev); 487 /* Resume clock after posting */ 488 r300_clock_startup(rdev); 489 /* Initialize surface registers */ 490 radeon_surface_init(rdev); 491 492 rdev->accel_working = true; 493 r = rs400_startup(rdev); 494 if (r) { 495 rdev->accel_working = false; 496 } 497 return r; 498 } 499 500 int rs400_suspend(struct radeon_device *rdev) 501 { 502 radeon_pm_suspend(rdev); 503 r100_cp_disable(rdev); 504 radeon_wb_disable(rdev); 505 r100_irq_disable(rdev); 506 rs400_gart_disable(rdev); 507 return 0; 508 } 509 510 void rs400_fini(struct radeon_device *rdev) 511 { 512 radeon_pm_fini(rdev); 513 r100_cp_fini(rdev); 514 radeon_wb_fini(rdev); 515 radeon_ib_pool_fini(rdev); 516 radeon_gem_fini(rdev); 517 rs400_gart_fini(rdev); 518 radeon_irq_kms_fini(rdev); 519 radeon_fence_driver_fini(rdev); 520 radeon_bo_fini(rdev); 521 radeon_atombios_fini(rdev); 522 kfree(rdev->bios); 523 rdev->bios = NULL; 524 } 525 526 int rs400_init(struct radeon_device *rdev) 527 { 528 int r; 529 530 /* Disable VGA */ 531 r100_vga_render_disable(rdev); 532 /* Initialize scratch registers */ 533 radeon_scratch_init(rdev); 534 /* Initialize surface registers */ 535 radeon_surface_init(rdev); 536 /* TODO: disable VGA need to use VGA request */ 537 /* restore some register to sane defaults */ 538 r100_restore_sanity(rdev); 539 /* BIOS*/ 540 if (!radeon_get_bios(rdev)) { 541 if (ASIC_IS_AVIVO(rdev)) 542 return -EINVAL; 543 } 544 if (rdev->is_atom_bios) { 545 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 546 return -EINVAL; 547 } else { 548 r = radeon_combios_init(rdev); 549 if (r) 550 return r; 551 } 552 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 553 if (radeon_asic_reset(rdev)) { 554 dev_warn(rdev->dev, 555 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 556 RREG32(R_000E40_RBBM_STATUS), 557 RREG32(R_0007C0_CP_STAT)); 558 } 559 /* check if cards are posted or not */ 560 if (radeon_boot_test_post_card(rdev) == false) 561 return -EINVAL; 562 563 /* Initialize clocks */ 564 radeon_get_clock_info(rdev->ddev); 565 /* initialize memory controller */ 566 rs400_mc_init(rdev); 567 /* Fence driver */ 568 r = radeon_fence_driver_init(rdev); 569 if (r) 570 return r; 571 /* Memory manager */ 572 r = radeon_bo_init(rdev); 573 if (r) 574 return r; 575 r = rs400_gart_init(rdev); 576 if (r) 577 return r; 578 r300_set_reg_safe(rdev); 579 580 /* Initialize power management */ 581 radeon_pm_init(rdev); 582 583 rdev->accel_working = true; 584 r = rs400_startup(rdev); 585 if (r) { 586 /* Somethings want wront with the accel init stop accel */ 587 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 588 r100_cp_fini(rdev); 589 radeon_wb_fini(rdev); 590 radeon_ib_pool_fini(rdev); 591 rs400_gart_fini(rdev); 592 radeon_irq_kms_fini(rdev); 593 rdev->accel_working = false; 594 } 595 return 0; 596 } 597
Indexes created Sat Sep 20 22:09:52 GMT 2025