Lines Matching refs:tmp
72 uint32_t tmp;
77 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
78 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
120 uint32_t tmp;
122 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
123 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
124 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
159 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
160 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
162 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
163 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
164 WREG32(RADEON_BUS_CNTL, tmp);
166 WREG32(RADEON_MC_AGP_LOCATION, tmp);
167 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
168 WREG32(RADEON_BUS_CNTL, tmp);
171 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
172 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
174 WREG32_MC(RS480_GART_BASE, tmp);
186 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
187 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
188 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
190 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
191 tmp |= RS480_GART_INDEX_REG_EN;
192 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
206 uint32_t tmp;
208 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
209 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
210 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
250 uint32_t tmp;
254 tmp = RREG32(RADEON_MC_STATUS);
255 if (tmp & RADEON_MC_IDLE) {
320 uint32_t tmp;
322 tmp = RREG32(RADEON_HOST_PATH_CNTL);
323 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
324 tmp = RREG32(RADEON_BUS_CNTL);
325 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
326 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
327 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
329 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
330 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
331 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
332 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
333 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
334 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
335 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
336 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
337 tmp = RREG32(RS690_HDP_FB_LOCATION);
338 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
340 tmp = RREG32(RADEON_AGP_BASE);
341 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
342 tmp = RREG32(RS480_AGP_BASE_2);
343 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
344 tmp = RREG32(RADEON_MC_AGP_LOCATION);
345 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
347 tmp = RREG32_MC(RS480_GART_BASE);
348 seq_printf(m, "GART_BASE 0x%08x\n", tmp);
349 tmp = RREG32_MC(RS480_GART_FEATURE_ID);
350 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
351 tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
352 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
353 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
354 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
355 tmp = RREG32_MC(0x5F);
356 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
357 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
358 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
359 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
360 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
361 tmp = RREG32_MC(0x3B);
362 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
363 tmp = RREG32_MC(0x3C);
364 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
365 tmp = RREG32_MC(0x30);
366 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
367 tmp = RREG32_MC(0x31);
368 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
369 tmp = RREG32_MC(0x32);
370 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
371 tmp = RREG32_MC(0x33);
372 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
373 tmp = RREG32_MC(0x34);
374 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
375 tmp = RREG32_MC(0x35);
376 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
377 tmp = RREG32_MC(0x36);
378 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
379 tmp = RREG32_MC(0x37);
380 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
Indexes created Mon Oct 20 05:10:11 GMT 2025