Home | History | Annotate | Download | only in ena-com

Lines Matching defs:aenq

165 	struct ena_com_aenq *aenq = &dev->aenq;
169 	dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
172 			aenq->entries,
173 			aenq->dma_addr,
174 			aenq->mem_handle);
176 	if (!aenq->entries) {
181 	aenq->head = aenq->q_depth;
182 	aenq->phase = 1;
184 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
185 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
191 	aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
198 		ena_trc_err("aenq handlers pointer is NULL\n");
202 	aenq->aenq_handlers = aenq_handlers;
1396 	 * XXX: workaround for missing synchronization mechanism of AENQ handler
1452 	u16 depth = ena_dev->aenq.q_depth;
1454 	ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1472 		ena_trc_info("Can't get aenq configuration\n");
1476 	if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1477 		ena_trc_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1478 			     get_resp.u.aenq.supported_groups,
1489 	cmd.u.aenq.enabled_groups = groups_flag;
1498 		ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1585 	struct ena_com_aenq *aenq = &ena_dev->aenq;
1616 	size = ADMIN_AENQ_SIZE(aenq->q_depth);
1617 	if (ena_dev->aenq.entries)
1618 		ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1619 				      aenq->dma_addr, aenq->mem_handle);
1620 	aenq->entries = NULL;
1899 	memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1900 	       sizeof(get_resp.u.aenq));
1946 	struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1955  * handles the aenq incoming events.
1962 	struct ena_com_aenq *aenq  = &dev->aenq;
1968 	masked_head = aenq->head & (aenq->q_depth - 1);
1969 	phase = aenq->phase;
1970 	aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1978 		ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1992 		if (unlikely(masked_head == aenq->q_depth)) {
1996 		aenq_e = &aenq->entries[masked_head];
2000 	aenq->head += processed;
2001 	aenq->phase = phase;
2003 	/* Don't update aenq doorbell if there weren't any processed events */
2007 	/* write the aenq doorbell after all AENQ descriptors were read */
2009 	ENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);