Lines Matching refs:admin_queue
236 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
247 queue_size_mask = admin_queue->q_depth - 1;
249 tail_masked = admin_queue->sq.tail & queue_size_mask;
252 cnt = ATOMIC32_READ(&admin_queue->outstanding_cmds);
253 if (cnt >= admin_queue->q_depth) {
255 admin_queue->stats.out_of_space++;
259 cmd_id = admin_queue->curr_cmd_id;
261 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
267 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
278 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
280 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
283 admin_queue->sq.tail++;
284 admin_queue->stats.submitted_cmd++;
286 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
287 admin_queue->sq.phase = !admin_queue->sq.phase;
289 ENA_DB_SYNC(&admin_queue->sq.mem_handle);
290 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
291 admin_queue->sq.db_addr);
317 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
326 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
327 if (unlikely(!admin_queue->running_state)) {
328 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
331 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
336 admin_queue->running_state = false;
337 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
464 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
473 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
476 admin_queue->running_state = false;
486 if (!admin_queue->polling)
490 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
497 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
498 phase = admin_queue->cq.phase;
500 cqe = &admin_queue->cq.entries[head_masked];
509 ena_com_handle_single_admin_completion(admin_queue, cqe);
513 if (unlikely(head_masked == admin_queue->q_depth)) {
518 cqe = &admin_queue->cq.entries[head_masked];
521 admin_queue->cq.head += comp_num;
522 admin_queue->cq.phase = phase;
523 admin_queue->sq.head += comp_num;
524 admin_queue->stats.completed_cmd += comp_num;
553 struct ena_com_admin_queue *admin_queue)
558 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
561 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
562 ena_com_handle_admin_completion(admin_queue);
563 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
571 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
572 admin_queue->stats.no_completion++;
573 admin_queue->running_state = false;
574 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
585 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
586 admin_queue->stats.aborted_cmd++;
587 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
597 comp_ctxt_release(admin_queue, comp_ctx);
671 struct ena_com_admin_queue *admin_queue)
677 admin_queue->completion_timeout);
685 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
686 ena_com_handle_admin_completion(admin_queue);
687 admin_queue->stats.no_completion++;
688 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
697 admin_queue->running_state = false;
704 comp_ctxt_release(admin_queue, comp_ctx);
783 struct ena_com_admin_queue *admin_queue)
785 if (admin_queue->polling)
787 admin_queue);
790 admin_queue);
796 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
816 ret = ena_com_execute_admin_command(admin_queue,
908 struct ena_com_admin_queue *admin_queue;
918 admin_queue = &ena_dev->admin_queue;
940 ret = ena_com_execute_admin_command(admin_queue,
1105 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1147 ret = ena_com_execute_admin_command(admin_queue,
1262 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1271 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1284 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1286 if (admin_queue->running_state)
1299 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1324 ret = ena_com_execute_admin_command(admin_queue,
1372 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1376 if (!admin_queue->comp_ctx)
1379 for (i = 0; i < admin_queue->q_depth; i++) {
1380 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1392 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1401 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1402 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1403 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1405 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1407 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1413 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1423 ret = ena_com_execute_admin_command(admin_queue,
1437 return ena_dev->admin_queue.running_state;
1442 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1445 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1446 ena_dev->admin_queue.running_state = state;
1447 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1464 struct ena_com_admin_queue *admin_queue;
1484 admin_queue = &ena_dev->admin_queue;
1491 ret = ena_com_execute_admin_command(admin_queue,
1582 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1583 struct ena_com_admin_cq *cq = &admin_queue->cq;
1584 struct ena_com_admin_sq *sq = &admin_queue->sq;
1589 ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1591 if (admin_queue->comp_ctx) {
1594 for (i = 0; i < admin_queue->q_depth; i++) {
1595 struct ena_comp_ctx *comp_ctx = get_comp_ctxt(admin_queue, i, false);
1600 s = admin_queue->q_depth * sizeof(struct ena_comp_ctx);
1601 ENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx, s);
1603 admin_queue->comp_ctx = NULL;
1604 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1610 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1631 ena_dev->admin_queue.polling = polling;
1697 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1717 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1719 admin_queue->bus = ena_dev->bus;
1720 admin_queue->q_dmadev = ena_dev->dmadev;
1721 admin_queue->polling = false;
1722 admin_queue->curr_cmd_id = 0;
1724 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1727 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1729 ret = ena_com_init_comp_ctxt(admin_queue);
1733 ret = ena_com_admin_init_sq(admin_queue);
1737 ret = ena_com_admin_init_cq(admin_queue);
1741 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1744 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1745 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1750 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1751 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1757 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1763 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1774 admin_queue->running_state = true;
1937 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2088 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2090 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2101 struct ena_com_admin_queue *admin_queue;
2104 admin_queue = &ena_dev->admin_queue;
2110 ret = ena_com_execute_admin_command(admin_queue,
2184 struct ena_com_admin_queue *admin_queue;
2195 admin_queue = &ena_dev->admin_queue;
2202 ret = ena_com_execute_admin_command(admin_queue,
2234 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2279 ret = ena_com_execute_admin_command(admin_queue,
2398 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2431 ret = ena_com_execute_admin_command(admin_queue,
2558 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2597 ret = ena_com_execute_admin_command(admin_queue,
2743 struct ena_com_admin_queue *admin_queue;
2754 admin_queue = &ena_dev->admin_queue;
2777 ret = ena_com_execute_admin_command(admin_queue,
Indexes created Tue Sep 30 06:09:59 GMT 2025