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Lines Matching defs:pModal

96     MODAL_EEP4K_HEADER	*pModal;
120     pModal = &pEepData->modalHeader;
125         ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
250     const MODAL_EEP4K_HEADER *pModal;
255     pModal = &eep->modalHeader;
257     OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
258     OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]);
262         	SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
263         	SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
269 		    pModal->swSettleHt40);
271 	txRxAttenLocal = pModal->txRxAttenCh[0];
274 	    pModal->bswMargin[0]);
276 	    pModal->bswAtten[0]);
278 	    pModal->xatten2Margin[0]);
280 	    pModal->xatten2Db[0]);
284 	    AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
286 	    AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
288 	    AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]);
290 	    AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
296         AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
301         AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);