Lines Matching refs:xd0
285 { "MEM_UOPS_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
286 { "MEM_UOPS_RETIRED.ALL_STORES", 0xd0, 0x82, true },
287 { "MEM_UOPS_RETIRED.ALL", 0xd0, 0x83, true },
288 { "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0xd0, 0x11, true },
289 { "MEM_UOPS_RETIRED.DTLB_MISS_STORES", 0xd0, 0x12, true },
290 { "MEM_UOPS_RETIRED.DTLB_MISS", 0xd0, 0x13, true },
291 { "MEM_UOPS_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
292 { "MEM_UOPS_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
293 { "MEM_UOPS_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
294 { "MEM_UOPS_RETIRED.SPLIT", 0xd0, 0x43, true },
489 { "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xd0, 0x11, true },
490 { "MEM_INST_RETIRED.STLB_MISS_STORES", 0xd0, 0x12, true },
491 { "MEM_INST_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
492 { "MEM_INST_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
493 { "MEM_INST_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
494 { "MEM_INST_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
495 { "MEM_INST_RETIRED.ALL_STORES", 0xd0, 0x82, true },
722 { "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xd0, 0x11, true },
723 { "MEM_INST_RETIRED.STLB_MISS_STORES", 0xd0, 0x12, true },
724 { "MEM_INST_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
725 { "MEM_INST_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
726 { "MEM_INST_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
727 { "MEM_INST_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
728 { "MEM_INST_RETIRED.ALL_STORES", 0xd0, 0x82, true },
916 { "ins-empty", 0xd0, 0x00, true },
Indexes created Mon Oct 13 08:09:50 GMT 2025