Lines Matching refs:perf
35 const struct panfrost_perf *perf)
37 assert(counter->offset < perf->n_counter_values);
38 uint32_t ret = perf->counter_values[counter->offset];
41 if (counter->category == &perf->cfg->categories[PAN_SHADER_CORE_INDEX]) {
42 for (uint32_t core = 1; core < perf->dev->core_count; ++core) {
43 ret += perf->counter_values[counter->offset + PAN_COUNTERS_PER_CATEGORY * core];
79 panfrost_perf_init(struct panfrost_perf *perf, struct panfrost_device *dev)
81 perf->dev = dev;
82 perf->cfg = get_perf_config(dev->gpu_id);
87 perf->n_counter_values = PAN_COUNTERS_PER_CATEGORY * n_blocks;
88 perf->counter_values = ralloc_array(perf, uint32_t, perf->n_counter_values);
92 panfrost_perf_query(struct panfrost_perf *perf, uint32_t enable)
95 return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_ENABLE, &perfcnt_enable);
99 panfrost_perf_enable(struct panfrost_perf *perf)
101 return panfrost_perf_query(perf, 1 /* enable */);
105 panfrost_perf_disable(struct panfrost_perf *perf)
107 return panfrost_perf_query(perf, 0 /* disable */);
111 panfrost_perf_dump(struct panfrost_perf *perf)
114 struct drm_panfrost_perfcnt_dump perfcnt_dump = {(uint64_t)(uintptr_t)perf->counter_values};
115 return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_DUMP, &perfcnt_dump);