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Lines Matching refs:Dst

68  * - for each e, e->Dst has been processed, but not e->Org
69 * - each edge e satisfies VertLeq(e->Dst,event) && VertLeq(event,e->Org)
128 if( e1->Dst == event ) {
129 if( e2->Dst == event ) {
134 return EdgeSign( e2->Dst, e1->Org, e2->Org ) <= 0;
136 return EdgeSign( e1->Dst, e2->Org, e1->Org ) >= 0;
138 return EdgeSign( e2->Dst, event, e2->Org ) <= 0;
140 if( e2->Dst == event ) {
141 return EdgeSign( e1->Dst, event, e1->Org ) >= 0;
145 t1 = EdgeEval( e1->Dst, event, e1->Org );
146 t2 = EdgeEval( e2->Dst, event, e2->Org );
204 GLUvertex *dst = reg->eUp->Dst;
209 } while( reg->eUp->Dst == dst );
361 assert( VertLeq( e->Org, e->Dst ));
454 static void VertexWeights( GLUvertex *isect, GLUvertex *org, GLUvertex *dst,
460 * splits the weight between its org and dst according to the
465 GLdouble t2 = VertL1dist( dst, isect );
469 isect->coords[0] += weights[0]*org->coords[0] + weights[1]*dst->coords[0];
470 isect->coords[1] += weights[0]*org->coords[1] + weights[1]*dst->coords[1];
471 isect->coords[2] += weights[0]*org->coords[2] + weights[1]*dst->coords[2];
531 if( EdgeSign( eLo->Dst, eUp->Org, eLo->Org ) > 0 ) return FALSE;
546 if( EdgeSign( eUp->Dst, eLo->Org, eUp->Org ) < 0 ) return FALSE;
561 * eUp->Dst is above eLo, or eLo->Dst is below eUp (depending on which
566 * suppose at one point we checked eUp and eLo, and decided that eUp->Dst
569 * the test so that now eUp->Dst is incident to eLo, or barely below it.
583 assert( ! VertEq( eUp->Dst, eLo->Dst ));
585 if( VertLeq( eUp->Dst, eLo->Dst )) {
586 if( EdgeSign( eUp->Dst, eLo->Dst, eUp->Org ) < 0 ) return FALSE;
588 /* eLo->Dst is above eUp, so splice eLo->Dst into eUp */
597 if( EdgeSign( eLo->Dst, eUp->Dst, eLo->Org ) > 0 ) return FALSE;
599 /* eUp->Dst is below eLo, so splice eUp->Dst into eLo */
626 GLUvertex *dstUp = eUp->Dst;
627 GLUvertex *dstLo = eLo->Dst;
799 if( eUp->Dst != eLo->Dst ) {
800 /* Check that the edge ordering is obeyed at the Dst vertices. */
821 if( eUp->Dst != eLo->Dst
823 && (eUp->Dst == tess->event || eLo->Dst == tess->event) )
844 if( eUp->Org == eLo->Org && eUp->Dst == eLo->Dst ) {
896 if( eUp->Dst != eLo->Dst ) {
970 if( ! VertEq( e->Dst, vEvent )) {
983 /* vEvent coincides with e->Dst, which has already been processed.
992 /* Here e->Dst has only a single fixable edge going right.
1002 /* e->Dst had no left-going edges -- indicate this to AddRightEdges() */
1041 if( EdgeSign( eUp->Dst, vEvent, eUp->Org ) == 0 ) {
1047 * e->Dst is the vertex that we will connect to vEvent.
1049 reg = VertLeq( eLo->Dst, eUp->Dst ) ? regUp : regLo;
1151 e->Dst->s = -SENTINEL_COORD;
1152 e->Dst->t = t;
1153 tess->event = e->Dst; /* initialize it */
1220 if( VertEq( e->Org, e->Dst ) && e->Lnext->Lnext != e ) {