Lines Matching defs:src_obj

69     struct r600_accel_object src_obj, dst_obj;
161 src_obj.pitch = pPriv->src_pitch;
162 src_obj.width = pPriv->w;
163 src_obj.height = pPriv->h;
164 src_obj.bpp = 16;
165 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
166 src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
167 src_obj.tiling_flags = 0;
168 src_obj.surface = NULL;
176 &src_obj,
239 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
243 tex_res.w = accel_state->src_obj[0].width;
244 tex_res.h = accel_state->src_obj[0].height;
245 tex_res.pitch = accel_state->src_obj[0].pitch;
251 tex_res.bo = accel_state->src_obj[0].bo;
252 tex_res.mip_bo = accel_state->src_obj[0].bo;
266 if (accel_state->src_obj[0].tiling_flags == 0)
268 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
287 tex_res.w = accel_state->src_obj[0].width >> 1;
288 tex_res.h = accel_state->src_obj[0].height >> 1;
289 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
299 if (accel_state->src_obj[0].tiling_flags == 0)
301 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
310 tex_res.w = accel_state->src_obj[0].width >> 1;
311 tex_res.h = accel_state->src_obj[0].height >> 1;
312 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
322 if (accel_state->src_obj[0].tiling_flags == 0)
324 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
333 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
337 tex_res.w = accel_state->src_obj[0].width;
338 tex_res.h = accel_state->src_obj[0].height;
339 tex_res.pitch = accel_state->src_obj[0].pitch >> 1;
345 tex_res.bo = accel_state->src_obj[0].bo;
346 tex_res.mip_bo = accel_state->src_obj[0].bo;
362 if (accel_state->src_obj[0].tiling_flags == 0)
364 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);