1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Author: Alex Deucher <alexander.deucher@amd.com> 24 * 25 */ 26 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include "xf86.h" 32 33#include "exa.h" 34 35#include "radeon.h" 36#include "radeon_reg.h" 37#include "r600_shader.h" 38#include "r600_reg.h" 39#include "r600_state.h" 40 41#include "radeon_video.h" 42 43#include <X11/extensions/Xv.h> 44#include "fourcc.h" 45 46#include "damage.h" 47 48#include "radeon_exa_shared.h" 49#include "radeon_vbo.h" 50 51/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces 52 note the difference to the parameters used in overlay are due 53 to 10bit vs. float calcs */ 54static REF_TRANSFORM trans[2] = 55{ 56 {1.1643, 0.0, 1.5960, -0.3918, -0.8129, 2.0172, 0.0}, /* BT.601 */ 57 {1.1643, 0.0, 1.7927, -0.2132, -0.5329, 2.1124, 0.0} /* BT.709 */ 58}; 59 60void 61R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) 62{ 63 RADEONInfoPtr info = RADEONPTR(pScrn); 64 struct radeon_accel_state *accel_state = info->accel_state; 65 PixmapPtr pPixmap = pPriv->pPixmap; 66 BoxPtr pBox = REGION_RECTS(&pPriv->clip); 67 int nBox = REGION_NUM_RECTS(&pPriv->clip); 68 int dstxoff, dstyoff; 69 struct r600_accel_object src_obj, dst_obj; 70 cb_config_t cb_conf; 71 tex_resource_t tex_res; 72 tex_sampler_t tex_samp; 73 shader_config_t vs_conf, ps_conf; 74 /* 75 * y' = y - .0625 76 * u' = u - .5 77 * v' = v - .5; 78 * 79 * r = 1.1643 * y' + 0.0 * u' + 1.5958 * v' 80 * g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v' 81 * b = 1.1643 * y' + 2.017 * u' + 0.0 * v' 82 * 83 * DP3 might look like the straightforward solution 84 * but we'd need to move the texture yuv values in 85 * the same reg for this to work. Therefore use MADs. 86 * Brightness just adds to the off constant. 87 * Contrast is multiplication of luminance. 88 * Saturation and hue change the u and v coeffs. 89 * Default values (before adjustments - depend on colorspace): 90 * yco = 1.1643 91 * uco = 0, -0.39173, 2.017 92 * vco = 1.5958, -0.8129, 0 93 * off = -0.0625 * yco + -0.5 * uco[r] + -0.5 * vco[r], 94 * -0.0625 * yco + -0.5 * uco[g] + -0.5 * vco[g], 95 * -0.0625 * yco + -0.5 * uco[b] + -0.5 * vco[b], 96 * 97 * temp = MAD(yco, yuv.yyyy, off) 98 * temp = MAD(uco, yuv.uuuu, temp) 99 * result = MAD(vco, yuv.vvvv, temp) 100 */ 101 /* TODO: calc consts in the shader */ 102 const float Loff = -0.0627; 103 const float Coff = -0.502; 104 float uvcosf, uvsinf; 105 float yco; 106 float uco[3], vco[3], off[3]; 107 float bright, cont, gamma; 108 int ref = pPriv->transform_index; 109 float ps_alu_consts[12]; 110 float vs_alu_consts[4]; 111 112 cont = RTFContrast(pPriv->contrast); 113 bright = RTFBrightness(pPriv->brightness); 114 gamma = (float)pPriv->gamma / 1000.0; 115 uvcosf = RTFSaturation(pPriv->saturation) * cos(RTFHue(pPriv->hue)); 116 uvsinf = RTFSaturation(pPriv->saturation) * sin(RTFHue(pPriv->hue)); 117 /* overlay video also does pre-gamma contrast/sat adjust, should we? */ 118 119 yco = trans[ref].RefLuma * cont; 120 uco[0] = -trans[ref].RefRCr * uvsinf; 121 uco[1] = trans[ref].RefGCb * uvcosf - trans[ref].RefGCr * uvsinf; 122 uco[2] = trans[ref].RefBCb * uvcosf; 123 vco[0] = trans[ref].RefRCr * uvcosf; 124 vco[1] = trans[ref].RefGCb * uvsinf + trans[ref].RefGCr * uvcosf; 125 vco[2] = trans[ref].RefBCb * uvsinf; 126 off[0] = Loff * yco + Coff * (uco[0] + vco[0]) + bright; 127 off[1] = Loff * yco + Coff * (uco[1] + vco[1]) + bright; 128 off[2] = Loff * yco + Coff * (uco[2] + vco[2]) + bright; 129 130 // XXX 131 gamma = 1.0; 132 133 /* setup the ps consts */ 134 ps_alu_consts[0] = off[0]; 135 ps_alu_consts[1] = off[1]; 136 ps_alu_consts[2] = off[2]; 137 ps_alu_consts[3] = yco; 138 139 ps_alu_consts[4] = uco[0]; 140 ps_alu_consts[5] = uco[1]; 141 ps_alu_consts[6] = uco[2]; 142 ps_alu_consts[7] = gamma; 143 144 ps_alu_consts[8] = vco[0]; 145 ps_alu_consts[9] = vco[1]; 146 ps_alu_consts[10] = vco[2]; 147 ps_alu_consts[11] = 0.0; 148 149 CLEAR (cb_conf); 150 CLEAR (tex_res); 151 CLEAR (tex_samp); 152 CLEAR (vs_conf); 153 CLEAR (ps_conf); 154 155 dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon; 156 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap); 157 dst_obj.surface = radeon_get_pixmap_surface(pPixmap); 158 159 dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8); 160 161 src_obj.pitch = pPriv->src_pitch; 162 src_obj.width = pPriv->w; 163 src_obj.height = pPriv->h; 164 src_obj.bpp = 16; 165 src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; 166 src_obj.bo = pPriv->src_bo[pPriv->currentBuffer]; 167 src_obj.tiling_flags = 0; 168 src_obj.surface = NULL; 169 170 dst_obj.width = pPixmap->drawable.width; 171 dst_obj.height = pPixmap->drawable.height; 172 dst_obj.bpp = pPixmap->drawable.bitsPerPixel; 173 dst_obj.domain = RADEON_GEM_DOMAIN_VRAM; 174 175 if (!R600SetAccelState(pScrn, 176 &src_obj, 177 NULL, 178 &dst_obj, 179 accel_state->xv_vs_offset, accel_state->xv_ps_offset, 180 3, 0xffffffff)) 181 return; 182 183#ifdef COMPOSITE 184 dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; 185 dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; 186#else 187 dstxoff = 0; 188 dstyoff = 0; 189#endif 190 191 radeon_vbo_check(pScrn, &accel_state->vbo, 16); 192 radeon_cp_start(pScrn); 193 194 r600_set_default_state(pScrn); 195 196 r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 197 r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 198 r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height); 199 200 /* PS bool constant */ 201 switch(pPriv->id) { 202 case FOURCC_YV12: 203 case FOURCC_I420: 204 r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (1 << 0)); 205 break; 206 case FOURCC_UYVY: 207 case FOURCC_YUY2: 208 default: 209 r600_set_bool_consts(pScrn, SQ_BOOL_CONST_ps, (0 << 0)); 210 break; 211 } 212 213 /* Shader */ 214 vs_conf.shader_addr = accel_state->vs_mc_addr; 215 vs_conf.shader_size = accel_state->vs_size; 216 vs_conf.num_gprs = 2; 217 vs_conf.stack_size = 0; 218 vs_conf.bo = accel_state->shaders_bo; 219 r600_vs_setup(pScrn, &vs_conf, RADEON_GEM_DOMAIN_VRAM); 220 221 ps_conf.shader_addr = accel_state->ps_mc_addr; 222 ps_conf.shader_size = accel_state->ps_size; 223 ps_conf.num_gprs = 3; 224 ps_conf.stack_size = 1; 225 ps_conf.uncached_first_inst = 1; 226 ps_conf.clamp_consts = 0; 227 ps_conf.export_mode = 2; 228 ps_conf.bo = accel_state->shaders_bo; 229 r600_ps_setup(pScrn, &ps_conf, RADEON_GEM_DOMAIN_VRAM); 230 231 /* PS alu constants */ 232 r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_ps, 233 sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts); 234 235 /* Texture */ 236 switch(pPriv->id) { 237 case FOURCC_YV12: 238 case FOURCC_I420: 239 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; 240 241 /* Y texture */ 242 tex_res.id = 0; 243 tex_res.w = accel_state->src_obj[0].width; 244 tex_res.h = accel_state->src_obj[0].height; 245 tex_res.pitch = accel_state->src_obj[0].pitch; 246 tex_res.depth = 0; 247 tex_res.dim = SQ_TEX_DIM_2D; 248 tex_res.base = 0; 249 tex_res.mip_base = 0; 250 tex_res.size = accel_state->src_size[0]; 251 tex_res.bo = accel_state->src_obj[0].bo; 252 tex_res.mip_bo = accel_state->src_obj[0].bo; 253 tex_res.surface = NULL; 254 255 tex_res.format = FMT_8; 256 tex_res.dst_sel_x = SQ_SEL_X; /* Y */ 257 tex_res.dst_sel_y = SQ_SEL_1; 258 tex_res.dst_sel_z = SQ_SEL_1; 259 tex_res.dst_sel_w = SQ_SEL_1; 260 261 tex_res.request_size = 1; 262 tex_res.base_level = 0; 263 tex_res.last_level = 0; 264 tex_res.perf_modulation = 0; 265 tex_res.interlaced = 0; 266 if (accel_state->src_obj[0].tiling_flags == 0) 267 tex_res.tile_mode = 1; 268 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 269 270 /* Y sampler */ 271 tex_samp.id = 0; 272 tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; 273 tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; 274 tex_samp.clamp_z = SQ_TEX_WRAP; 275 276 /* xxx: switch to bicubic */ 277 tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; 278 tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; 279 280 tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; 281 tex_samp.mip_filter = 0; /* no mipmap */ 282 r600_set_tex_sampler(pScrn, &tex_samp); 283 284 /* U or V texture */ 285 tex_res.id = 1; 286 tex_res.format = FMT_8; 287 tex_res.w = accel_state->src_obj[0].width >> 1; 288 tex_res.h = accel_state->src_obj[0].height >> 1; 289 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); 290 tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ 291 tex_res.dst_sel_y = SQ_SEL_1; 292 tex_res.dst_sel_z = SQ_SEL_1; 293 tex_res.dst_sel_w = SQ_SEL_1; 294 tex_res.interlaced = 0; 295 296 tex_res.base = pPriv->planev_offset; 297 tex_res.mip_base = pPriv->planev_offset; 298 tex_res.size = tex_res.pitch * (pPriv->h >> 1); 299 if (accel_state->src_obj[0].tiling_flags == 0) 300 tex_res.tile_mode = 1; 301 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 302 303 /* U or V sampler */ 304 tex_samp.id = 1; 305 r600_set_tex_sampler(pScrn, &tex_samp); 306 307 /* U or V texture */ 308 tex_res.id = 2; 309 tex_res.format = FMT_8; 310 tex_res.w = accel_state->src_obj[0].width >> 1; 311 tex_res.h = accel_state->src_obj[0].height >> 1; 312 tex_res.pitch = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align); 313 tex_res.dst_sel_x = SQ_SEL_X; /* V or U */ 314 tex_res.dst_sel_y = SQ_SEL_1; 315 tex_res.dst_sel_z = SQ_SEL_1; 316 tex_res.dst_sel_w = SQ_SEL_1; 317 tex_res.interlaced = 0; 318 319 tex_res.base = pPriv->planeu_offset; 320 tex_res.mip_base = pPriv->planeu_offset; 321 tex_res.size = tex_res.pitch * (pPriv->h >> 1); 322 if (accel_state->src_obj[0].tiling_flags == 0) 323 tex_res.tile_mode = 1; 324 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 325 326 /* UV sampler */ 327 tex_samp.id = 2; 328 r600_set_tex_sampler(pScrn, &tex_samp); 329 break; 330 case FOURCC_UYVY: 331 case FOURCC_YUY2: 332 default: 333 accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h; 334 335 /* YUV texture */ 336 tex_res.id = 0; 337 tex_res.w = accel_state->src_obj[0].width; 338 tex_res.h = accel_state->src_obj[0].height; 339 tex_res.pitch = accel_state->src_obj[0].pitch >> 1; 340 tex_res.depth = 0; 341 tex_res.dim = SQ_TEX_DIM_2D; 342 tex_res.base = 0; 343 tex_res.mip_base = 0; 344 tex_res.size = accel_state->src_size[0]; 345 tex_res.bo = accel_state->src_obj[0].bo; 346 tex_res.mip_bo = accel_state->src_obj[0].bo; 347 348 if (pPriv->id == FOURCC_UYVY) 349 tex_res.format = FMT_GB_GR; 350 else 351 tex_res.format = FMT_BG_RG; 352 tex_res.dst_sel_x = SQ_SEL_Y; 353 tex_res.dst_sel_y = SQ_SEL_X; 354 tex_res.dst_sel_z = SQ_SEL_Z; 355 tex_res.dst_sel_w = SQ_SEL_1; 356 357 tex_res.request_size = 1; 358 tex_res.base_level = 0; 359 tex_res.last_level = 0; 360 tex_res.perf_modulation = 0; 361 tex_res.interlaced = 0; 362 if (accel_state->src_obj[0].tiling_flags == 0) 363 tex_res.tile_mode = 1; 364 r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain); 365 366 /* YUV sampler */ 367 tex_samp.id = 0; 368 tex_samp.clamp_x = SQ_TEX_CLAMP_LAST_TEXEL; 369 tex_samp.clamp_y = SQ_TEX_CLAMP_LAST_TEXEL; 370 tex_samp.clamp_z = SQ_TEX_WRAP; 371 372 /* xxx: switch to bicubic */ 373 tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR; 374 tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_BILINEAR; 375 376 tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE; 377 tex_samp.mip_filter = 0; /* no mipmap */ 378 r600_set_tex_sampler(pScrn, &tex_samp); 379 380 break; 381 } 382 383 cb_conf.id = 0; 384 cb_conf.w = accel_state->dst_obj.pitch; 385 cb_conf.h = accel_state->dst_obj.height; 386 cb_conf.base = 0; 387 cb_conf.bo = accel_state->dst_obj.bo; 388 cb_conf.surface = accel_state->dst_obj.surface; 389 390 switch (accel_state->dst_obj.bpp) { 391 case 16: 392 if (pPixmap->drawable.depth == 15) { 393 cb_conf.format = COLOR_1_5_5_5; 394 cb_conf.comp_swap = 1; /* ARGB */ 395 } else { 396 cb_conf.format = COLOR_5_6_5; 397 cb_conf.comp_swap = 2; /* RGB */ 398 } 399#if X_BYTE_ORDER == X_BIG_ENDIAN 400 cb_conf.endian = ENDIAN_8IN16; 401#endif 402 break; 403 case 32: 404 cb_conf.format = COLOR_8_8_8_8; 405 cb_conf.comp_swap = 1; /* ARGB */ 406#if X_BYTE_ORDER == X_BIG_ENDIAN 407 cb_conf.endian = ENDIAN_8IN32; 408#endif 409 break; 410 default: 411 return; 412 } 413 414 cb_conf.source_format = 1; 415 cb_conf.blend_clamp = 1; 416 cb_conf.pmask = 0xf; 417 cb_conf.rop = 3; 418 if (accel_state->dst_obj.tiling_flags == 0) 419 cb_conf.array_mode = 1; 420 r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain); 421 422 r600_set_spi(pScrn, (1 - 1), 1); 423 424 vs_alu_consts[0] = 1.0 / pPriv->w; 425 vs_alu_consts[1] = 1.0 / pPriv->h; 426 vs_alu_consts[2] = 0.0; 427 vs_alu_consts[3] = 0.0; 428 429 /* VS alu constants */ 430 r600_set_alu_consts(pScrn, SQ_ALU_CONSTANT_vs, 431 sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts); 432 433 if (pPriv->vsync) { 434 xf86CrtcPtr crtc; 435 if (pPriv->desired_crtc) 436 crtc = pPriv->desired_crtc; 437 else 438 crtc = radeon_pick_best_crtc(pScrn, FALSE, 439 pPriv->drw_x, 440 pPriv->drw_x + pPriv->dst_w, 441 pPriv->drw_y, 442 pPriv->drw_y + pPriv->dst_h); 443 if (crtc) 444 r600_cp_wait_vline_sync(pScrn, pPixmap, 445 crtc, 446 pPriv->drw_y - crtc->y, 447 (pPriv->drw_y - crtc->y) + pPriv->dst_h); 448 } 449 450 while (nBox--) { 451 float srcX, srcY, srcw, srch; 452 int dstX, dstY, dstw, dsth; 453 float *vb; 454 455 456 dstX = pBox->x1 + dstxoff; 457 dstY = pBox->y1 + dstyoff; 458 dstw = pBox->x2 - pBox->x1; 459 dsth = pBox->y2 - pBox->y1; 460 461 srcX = pPriv->src_x; 462 srcX += ((pBox->x1 - pPriv->drw_x) * 463 pPriv->src_w) / (float)pPriv->dst_w; 464 srcY = pPriv->src_y; 465 srcY += ((pBox->y1 - pPriv->drw_y) * 466 pPriv->src_h) / (float)pPriv->dst_h; 467 468 srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w; 469 srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h; 470 471 vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16); 472 473 vb[0] = (float)dstX; 474 vb[1] = (float)dstY; 475 vb[2] = (float)srcX; 476 vb[3] = (float)srcY; 477 478 vb[4] = (float)dstX; 479 vb[5] = (float)(dstY + dsth); 480 vb[6] = (float)srcX; 481 vb[7] = (float)(srcY + srch); 482 483 vb[8] = (float)(dstX + dstw); 484 vb[9] = (float)(dstY + dsth); 485 vb[10] = (float)(srcX + srcw); 486 vb[11] = (float)(srcY + srch); 487 488 radeon_vbo_commit(pScrn, &accel_state->vbo); 489 490 pBox++; 491 } 492 493 r600_finish_op(pScrn, 16); 494 495 DamageDamageRegion(pPriv->pDraw, &pPriv->clip); 496} 497