Cross Reference: /xsrc/external/mit/xf86-video-ati-kms/dist/src/r600_textured

Lines Matching refs:accel_state
64     struct radeon_accel_state *accel_state = info->accel_state;
179 			   accel_state->xv_vs_offset, accel_state->xv_ps_offset,
191     radeon_vbo_check(pScrn, &accel_state->vbo, 16);
196     r600_set_generic_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
197     r600_set_screen_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
198     r600_set_window_scissor(pScrn, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
214     vs_conf.shader_addr         = accel_state->vs_mc_addr;
215     vs_conf.shader_size         = accel_state->vs_size;
218     vs_conf.bo                  = accel_state->shaders_bo;
221     ps_conf.shader_addr         = accel_state->ps_mc_addr;
222     ps_conf.shader_size         = accel_state->ps_size;
228     ps_conf.bo                  = accel_state->shaders_bo;
239 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
243 	tex_res.w                   = accel_state->src_obj[0].width;
244 	tex_res.h                   = accel_state->src_obj[0].height;
245 	tex_res.pitch               = accel_state->src_obj[0].pitch;
250 	tex_res.size                = accel_state->src_size[0];
251 	tex_res.bo                  = accel_state->src_obj[0].bo;
252 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
266 	if (accel_state->src_obj[0].tiling_flags == 0)
268 	r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
287 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
288 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
289 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
299 	if (accel_state->src_obj[0].tiling_flags == 0)
301 	r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
310 	tex_res.w                   = accel_state->src_obj[0].width >> 1;
311 	tex_res.h                   = accel_state->src_obj[0].height >> 1;
312 	tex_res.pitch               = RADEON_ALIGN(accel_state->src_obj[0].pitch >> 1, pPriv->hw_align);
322 	if (accel_state->src_obj[0].tiling_flags == 0)
324 	r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
333 	accel_state->src_size[0] = accel_state->src_obj[0].pitch * pPriv->h;
337 	tex_res.w                   = accel_state->src_obj[0].width;
338 	tex_res.h                   = accel_state->src_obj[0].height;
339 	tex_res.pitch               = accel_state->src_obj[0].pitch >> 1;
344 	tex_res.size                = accel_state->src_size[0];
345 	tex_res.bo                  = accel_state->src_obj[0].bo;
346 	tex_res.mip_bo              = accel_state->src_obj[0].bo;
362 	if (accel_state->src_obj[0].tiling_flags == 0)
364 	r600_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
384     cb_conf.w = accel_state->dst_obj.pitch;
385     cb_conf.h = accel_state->dst_obj.height;
387     cb_conf.bo = accel_state->dst_obj.bo;
388     cb_conf.surface = accel_state->dst_obj.surface;
390     switch (accel_state->dst_obj.bpp) {
418     if (accel_state->dst_obj.tiling_flags == 0)
420     r600_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
471 	vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
488 	radeon_vbo_commit(pScrn, &accel_state->vbo);