Lines Matching refs:OUT_RING_REG
227 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
228 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
229 OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
233 OUT_RING_REG(R300_GB_AA_CONFIG, 0);
234 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
235 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
239 OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
240 OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
242 OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
250 OUT_RING_REG(R300_GA_OFFSET, 0);
254 OUT_RING_REG(R300_SU_TEX_WRAP, 0);
255 OUT_RING_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
256 OUT_RING_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
257 OUT_RING_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
258 OUT_RING_REG(R300_SU_DEPTH_OFFSET, 0);
291 OUT_RING_REG(R300_VAP_VTX_STATE_CNTL, 0);
292 OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
295 OUT_RING_REG(R300_VAP_CNTL_STATUS, 0);
297 OUT_RING_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
298 OUT_RING_REG(R300_VAP_CNTL, vap_cntl);
299 OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
300 OUT_RING_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
301 OUT_RING_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
303 OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
316 OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
325 OUT_RING_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
326 OUT_RING_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
327 OUT_RING_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
328 OUT_RING_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
329 OUT_RING_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
330 OUT_RING_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
338 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0));
340 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
346 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
353 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
360 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
369 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
374 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
381 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
388 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
397 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
402 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
409 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
416 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
425 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
430 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
437 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
444 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
453 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
458 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
465 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
472 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
481 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
486 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
493 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
500 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
509 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
514 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
521 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
528 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
537 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
542 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
549 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
556 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
565 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
570 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
577 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
584 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
595 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9));
597 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
603 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
610 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
617 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
625 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
630 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
637 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
644 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
655 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11));
657 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
663 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
670 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
677 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
686 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
692 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
699 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
706 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
715 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
721 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
728 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
735 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG,
753 OUT_RING_REG(R300_RS_IP_0,
759 OUT_RING_REG(R300_RS_IP_1,
769 OUT_RING_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
773 OUT_RING_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
783 OUT_RING_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
788 OUT_RING_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
796 OUT_RING_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
800 OUT_RING_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
810 OUT_RING_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
811 OUT_RING_REG(R500_US_FC_CTRL, 0);
813 OUT_RING_REG(R300_US_W_FMT, 0);
814 OUT_RING_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
819 OUT_RING_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
824 OUT_RING_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
833 OUT_RING_REG(R300_FG_DEPTH_SRC, 0);
834 OUT_RING_REG(R300_FG_FOG_BLEND, 0);
835 OUT_RING_REG(R300_FG_ALPHA_FUNC, 0);
839 OUT_RING_REG(R300_RB3D_ABLENDCNTL, 0);
840 OUT_RING_REG(R300_RB3D_ZSTENCILCNTL, 0);
841 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
842 OUT_RING_REG(R300_RB3D_BW_CNTL, 0);
843 OUT_RING_REG(R300_RB3D_ZCNTL, 0);
844 OUT_RING_REG(R300_RB3D_ZTOP, 0);
845 OUT_RING_REG(R300_RB3D_ROPCNTL, 0);
847 OUT_RING_REG(R300_RB3D_AARESOLVE_CTL, 0);
848 OUT_RING_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
852 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
853 OUT_RING_REG(R300_RB3D_CCTL, 0);
854 OUT_RING_REG(R300_RB3D_DITHER_CTL, 0);
855 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
859 OUT_RING_REG(R300_SC_EDGERULE, 0xA5294A5);
862 OUT_RING_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
864 OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
867 OUT_RING_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
869 OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
872 OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA);
873 OUT_RING_REG(R300_SC_SCREENDOOR, 0xffffff);
879 OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
881 OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, 0);
883 OUT_RING_REG(R200_PP_CNTL_X, 0);
884 OUT_RING_REG(R200_PP_TXMULTI_CTL_0, 0);
885 OUT_RING_REG(R200_SE_VTX_STATE_CNTL, 0);
886 OUT_RING_REG(R200_SE_VTE_CNTL, 0);
887 OUT_RING_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
892 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, 0);
893 OUT_RING_REG(R200_RE_CNTL, 0);
894 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
895 OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
906 OUT_RING_REG(RADEON_SE_CNTL_STATUS, 0);
908 OUT_RING_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
909 OUT_RING_REG(RADEON_SE_COORD_FMT,
917 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
918 OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
961 OUT_RING_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */
966 OUT_RING_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */
972 OUT_RING_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE |
Indexes created Tue Jul 21 00:24:56 UTC 2026