Lines Matching refs:RT_regw
139 #define RT_regw(reg,data) theatre_write(t,(reg),(data))
370 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE));
374 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP));
424 RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17));
431 RT_regw(VIP_TC_SOURCE, 0x90000000);
432 RT_regw(VIP_TC_DESTINATION, 0x00000000);
433 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7));
460 RT_regw(VIP_TC_SOURCE, 0x00000000);
461 RT_regw(VIP_TC_DESTINATION, 0x10000000);
462 RT_regw(VIP_TC_COMMAND, 0xe0000006 | ((seg_list->num_bytes - 1) << 7));
481 RT_regw(VIP_TC_DOWNLOAD, data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE);
515 RT_regw(VIP_TC_SOURCE, 0x90000000);
516 RT_regw(VIP_TC_DESTINATION, 0x10000000);
517 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7));
593 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR);
598 RT_regw(VIP_FB_SCRATCH0, fb_scratch0);
600 RT_regw(VIP_FB_SCRATCH1, fb_scratch1);
606 RT_regw(VIP_FB_INT, data | VIP_FB_INT__INT_7);
625 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR);
1465 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE)
1907 RT_regw(VIP_DSP_PLL_CNTL, data);
1911 RT_regw(VIP_PLL_CNTL0, data);
1913 /* RT_regw(VIP_I2C_SLVCNTL, 0x249); */
1916 RT_regw(VIP_PLL_CNTL1, data);
1920 RT_regw(VIP_PLL_CNTL0, data);
1925 RT_regw(VIP_CLOCK_SEL_CNTL, data);
1929 RT_regw(VIP_MASTER_CNTL, data);
1931 RT_regw(VIP_MASTER_CNTL, data);
2246 RT_regw(VIP_CLKOUT_CNTL, 0x0);
2247 RT_regw(VIP_HCOUNT, 0x0);
2248 RT_regw(VIP_VCOUNT, 0x0);
2249 RT_regw(VIP_DFCOUNT, 0x0);
2251 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
2252 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
2254 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0);
2260 /* RT_regw(VIP_HW_DEBUG, 0x200); */
2261 /* RT_regw(VIP_INT_CNTL, 0x0);
2262 RT_regw(VIP_GPIO_INOUT, 0x10090000);
2263 RT_regw(VIP_GPIO_INOUT, 0x340b0000); */
2264 /* RT_regw(VIP_MASTER_CNTL, 0x6e8); */
2265 RT_regw(VIP_CLKOUT_CNTL, 0x29);
2267 RT_regw(VIP_HCOUNT, 0x1d1);
2268 RT_regw(VIP_VCOUNT, 0x1e3);
2270 RT_regw(VIP_HCOUNT, 0x322);
2271 RT_regw(VIP_VCOUNT, 0x151);
2273 RT_regw(VIP_DFCOUNT, 0x01);
2274 /* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */
2275 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */
2276 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039);
2277 /* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */
2278 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f);
2279 /* RT_regw(VIP_ADC_CNTL, 0x02a420a8);
2280 RT_regw(VIP_COMB_CNTL_0, 0x0d438083);
2281 RT_regw(VIP_COMB_CNTL_2, 0x06080102);
2282 RT_regw(VIP_HS_MINMAXWIDTH, 0x462f);
2286 RT_regw(VIP_HS_PULSE_WIDTH, 0x359);
2287 RT_regw(VIP_HS_PLL_ERROR, 0xab6);
2288 RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8);
2289 RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005);