1/************************************************************************************* 2 * 3 * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy of this 6 * software and associated documentation files (the "Software"), to deal in the Software 7 * without restriction, including without limitation the rights to use, copy, modify, 8 * merge, publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all copies or 12 * substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 15 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 16 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Except as contained in this notice, the name of the author shall not be used in advertising or 21 * otherwise to promote the sale, use or other dealings in this Software without prior written 22 * authorization from the author. 23 * 24 * $Log: theatre200.c,v $ 25 * Revision 1.1.1.4 2012/09/23 19:49:13 veego 26 * initial import of xf86-video-ati-6.14.6. 27 * 28 * NetBSD note: The libdrm requirement seems to be KMS related which we do 29 * not have. 30 * 31 * * 6.15.6 32 * This version requires the latest libdrm 2.4.36 release, and fixes a few 33 * other bugs seen since 6.14.5. 34 * * 6.14.5 35 * - add solid picture accel 36 * - tiling fixes 37 * - new pci ids 38 * - 6xx-9xx Xv improvements 39 * - support for upcoming xserver API changes 40 * - bug fixes 41 * 42 * Revision 1.6 2006/03/22 22:30:14 krh 43 * 2006-03-22 Kristian Høgsberg <krh@redhat.com> 44 * 45 * * src/theatre200.c: Convert use of xf86fopen() and other xf86 46 * wrapped libc symbols to use libc symbols directly. The xf86* 47 * versions aren't supposed to be used directly. 48 * 49 * * src/ *.c: Drop libc wrapper; don't include xf86_ansic.h and add 50 * includes now missing. 51 * 52 * Revision 1.4 2005/08/28 18:00:23 bogdand 53 * Modified the licens type from GPL to a X/MIT one 54 * 55 * Revision 1.3 2005/07/11 02:29:45 ajax 56 * Prep for modular builds by adding guarded #include "config.h" everywhere. 57 * 58 * Revision 1.2 2005/07/01 22:43:11 daniels 59 * Change all misc.h and os.h references to <X11/foo.h>. 60 * 61 * 62 ************************************************************************************/ 63 64#ifdef HAVE_CONFIG_H 65#include "config.h" 66#endif 67 68#include <stdio.h> 69#include <string.h> 70 71#include "xf86.h" 72#include "generic_bus.h" 73#include "radeon_reg.h" 74#include "radeon.h" 75#include "theatre_reg.h" 76#include "theatre200.h" 77#include "radeon_macros.h" 78 79#undef read 80#undef write 81#undef ioctl 82 83void DumpRageTheatreRegsByName(TheatrePtr t); 84 85static int DownloadMicrocode(TheatrePtr t); 86static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen); 87static void microc_clean(struct rt200_microc_data* microc_datap, int screen); 88static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); 89static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); 90 91static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); 92static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); 93//static uint32_t dsp_reset(TheatrePtr t); 94static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); 95static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); 96static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); 97static uint32_t dsp_video_standard_detection(TheatrePtr t); 98//static uint32_t dsp_get_signallockstatus(TheatrePtr t); 99//static uint32_t dsp_get_signallinenumber(TheatrePtr t); 100 101static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); 102static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); 103//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); 104static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); 105static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); 106static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); 107static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); 108static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); 109static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); 110//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); 111static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); 112static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); 113 114static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) 115{ 116 if(t->theatre_num<0)return FALSE; 117 return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); 118} 119 120static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) 121{ 122 if(t->theatre_num<0)return FALSE; 123 return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); 124} 125 126static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) 127{ 128 if(t->theatre_num<0)return FALSE; 129 return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); 130} 131 132static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) 133{ 134 if(t->theatre_num<0)return FALSE; 135 return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); 136} 137 138#define RT_regr(reg,data) theatre_read(t,(reg),(data)) 139#define RT_regw(reg,data) theatre_write(t,(reg),(data)) 140#define RT_fifor(fifo,data) theatre_fifo_read(t,(fifo),(data)) 141#define RT_fifow(fifo,count,data) theatre_fifo_write(t,(fifo),(count),(data)) 142#define VIP_TYPE "ATI VIP BUS" 143 144static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen) 145{ 146 FILE* file; 147 struct rt200_microc_head* microc_headp = µc_datap->microc_head; 148 struct rt200_microc_seg* seg_list = NULL; 149 struct rt200_microc_seg* curr_seg = NULL; 150 struct rt200_microc_seg* prev_seg = NULL; 151 int i; 152 153 if (micro_path == NULL) 154 return -1; 155 156 if (micro_type == NULL) 157 return -1; 158 159 file = fopen(micro_path, "r"); 160 if (file == NULL) { 161 ERROR_0("Cannot open microcode file\n"); 162 return -1; 163 } 164 165 if (!strcmp(micro_type, "BINARY")) 166 { 167 if (fread(microc_headp, sizeof(struct rt200_microc_head), 1, file) != 1) 168 { 169 ERROR("Cannot read header from file: %s\n", micro_path); 170 goto fail_exit; 171 } 172 173 DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); 174 175 if (microc_headp->num_seg == 0) 176 goto fail_exit; 177 178 for (i = 0; i < microc_headp->num_seg; i++) 179 { 180 int ret; 181 182 curr_seg = (struct rt200_microc_seg*)malloc(sizeof(struct rt200_microc_seg)); 183 if (curr_seg == NULL) 184 { 185 ERROR_0("Cannot allocate memory\n"); 186 goto fail_exit; 187 } 188 189 ret = fread(&curr_seg->num_bytes, 4, 1, file); 190 ret += fread(&curr_seg->download_dst, 4, 1, file); 191 ret += fread(&curr_seg->crc_val, 4, 1, file); 192 if (ret != 3) 193 { 194 ERROR("Cannot read segment from microcode file: %s\n", micro_path); 195 goto fail_exit; 196 } 197 198 curr_seg->data = (unsigned char*)malloc(curr_seg->num_bytes); 199 if (curr_seg->data == NULL) 200 { 201 ERROR_0("cannot allocate memory\n"); 202 goto fail_exit; 203 } 204 205 DEBUG("Microcode: segment number: %x\n", i); 206 DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); 207 DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); 208 DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); 209 210 if (seg_list) 211 { 212 prev_seg->next = curr_seg; 213 curr_seg->next = NULL; 214 prev_seg = curr_seg; 215 } 216 else 217 seg_list = prev_seg = curr_seg; 218 219 } 220 221 curr_seg = seg_list; 222 while (curr_seg) 223 { 224 if (fread(curr_seg->data, curr_seg->num_bytes, 1, file) != 1) 225 { 226 ERROR_0("Cannot read segment data\n"); 227 goto fail_exit; 228 } 229 230 curr_seg = curr_seg->next; 231 } 232 } 233 else if (!strcmp(micro_type, "ASCII")) 234 { 235 char tmp1[12], tmp2[12], tmp3[12], tmp4[12]; 236 unsigned int ltmp; 237 238 if ((fgets(tmp1, 12, file) != NULL) && 239 (fgets(tmp2, 12, file) != NULL) && 240 (fgets(tmp3, 12, file) != NULL) && 241 fgets(tmp4, 12, file) != NULL) 242 { 243 microc_headp->device_id = strtoul(tmp1, NULL, 16); 244 microc_headp->vendor_id = strtoul(tmp2, NULL, 16); 245 microc_headp->revision_id = strtoul(tmp3, NULL, 16); 246 microc_headp->num_seg = strtoul(tmp4, NULL, 16); 247 } 248 else 249 { 250 ERROR("Cannot read header from file: %s\n", micro_path); 251 goto fail_exit; 252 } 253 254 DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); 255 256 if (microc_headp->num_seg == 0) 257 goto fail_exit; 258 259 for (i = 0; i < microc_headp->num_seg; i++) 260 { 261 curr_seg = (struct rt200_microc_seg*)malloc(sizeof(struct rt200_microc_seg)); 262 if (curr_seg == NULL) 263 { 264 ERROR_0("Cannot allocate memory\n"); 265 goto fail_exit; 266 } 267 268 if (fgets(tmp1, 12, file) != NULL && 269 fgets(tmp2, 12, file) != NULL && 270 fgets(tmp3, 12, file) != NULL) 271 { 272 curr_seg->num_bytes = strtoul(tmp1, NULL, 16); 273 curr_seg->download_dst = strtoul(tmp2, NULL, 16); 274 curr_seg->crc_val = strtoul(tmp3, NULL, 16); 275 } 276 else 277 { 278 ERROR("Cannot read segment from microcode file: %s\n", micro_path); 279 goto fail_exit; 280 } 281 282 curr_seg->data = (unsigned char*)malloc(curr_seg->num_bytes); 283 if (curr_seg->data == NULL) 284 { 285 ERROR_0("cannot allocate memory\n"); 286 goto fail_exit; 287 } 288 289 DEBUG("Microcode: segment number: %x\n", i); 290 DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); 291 DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); 292 DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); 293 294 if (seg_list) 295 { 296 curr_seg->next = NULL; 297 prev_seg->next = curr_seg; 298 prev_seg = curr_seg; 299 } 300 else 301 seg_list = prev_seg = curr_seg; 302 } 303 304 curr_seg = seg_list; 305 while (curr_seg) 306 { 307 for ( i = 0; i < curr_seg->num_bytes; i+=4) 308 { 309 310 if (fgets(tmp1, 12, file) == NULL) 311 { 312 ERROR_0("Cannot read from file\n"); 313 goto fail_exit; 314 } 315 ltmp = strtoul(tmp1, NULL, 16); 316 317 *(unsigned int*)(curr_seg->data + i) = ltmp; 318 } 319 320 curr_seg = curr_seg->next; 321 } 322 323 } 324 else 325 { 326 ERROR("File type %s unknown\n", micro_type); 327 } 328 329 microc_datap->microc_seg_list = seg_list; 330 331 fclose(file); 332 return 0; 333 334fail_exit: 335 curr_seg = seg_list; 336 while(curr_seg) 337 { 338 free(curr_seg->data); 339 prev_seg = curr_seg; 340 curr_seg = curr_seg->next; 341 free(prev_seg); 342 } 343 fclose(file); 344 345 return -1; 346} 347 348static void microc_clean(struct rt200_microc_data* microc_datap, int screen) 349{ 350 struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; 351 struct rt200_microc_seg* prev_seg; 352 353 while(seg_list) 354 { 355 free(seg_list->data); 356 prev_seg = seg_list; 357 seg_list = seg_list->next; 358 free(prev_seg); 359 } 360} 361 362static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) 363{ 364 uint32_t data; 365 int i = 0; 366 int screen = t->VIP->pScrn->scrnIndex; 367 368 /* Map FIFOD to DSP Port I/O port */ 369 RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); 370 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE)); 371 372 /* The default endianess is LE. It matches the ost one for x86 */ 373 RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); 374 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP)); 375 376 /* Wait until Shuttle bus channel 14 is available */ 377 RT_regr(VIP_TC_STATUS, &data); 378 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 379 RT_regr(VIP_TC_STATUS, &data); 380 381 DEBUG_0("Microcode: dsp_init: channel 14 available\n"); 382 383 return 0; 384} 385 386static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) 387{ 388 struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; 389 uint8_t data8; 390 uint32_t data, fb_scratch0, fb_scratch1; 391 uint32_t i; 392 uint32_t tries = 0; 393 uint32_t result = 0; 394 uint32_t seg_id = 0; 395 int screen = t->VIP->pScrn->scrnIndex; 396 397 DEBUG("Microcode: before everything: %x\n", data8); 398 399 if (RT_fifor(0x000, &data8)) 400 DEBUG("Microcode: FIFO status0: %x\n", data8); 401 else 402 { 403 ERROR_0("Microcode: error reading FIFO status0\n"); 404 return -1; 405 } 406 407 408 if (RT_fifor(0x100, &data8)) 409 DEBUG("Microcode: FIFO status1: %x\n", data8); 410 else 411 { 412 ERROR_0("Microcode: error reading FIFO status1\n"); 413 return -1; 414 } 415 416 /* 417 * Download the Boot Code and CRC Checking Code (first segment) 418 */ 419 seg_id = 1; 420 while(result != DSP_OK && tries < 10) 421 { 422 /* Put DSP in reset before download (0x02) */ 423 RT_regr(VIP_TC_DOWNLOAD, &data); 424 RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17)); 425 426 /* 427 * Configure shuttle bus for tranfer between DSP I/O "Program Interface" 428 * and Program Memory at address 0 429 */ 430 431 RT_regw(VIP_TC_SOURCE, 0x90000000); 432 RT_regw(VIP_TC_DESTINATION, 0x00000000); 433 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); 434 435 /* Load first segment */ 436 DEBUG_0("Microcode: Loading first segment\n"); 437 438 if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) 439 { 440 ERROR_0("Microcode: write to FIFOD failed\n"); 441 return -1; 442 } 443 444 /* Wait until Shuttle bus channel 14 is available */ 445 i = data = 0; 446 RT_regr(VIP_TC_STATUS, &data); 447 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 448 RT_regr(VIP_TC_STATUS, &data); 449 450 if (i >= 10000) 451 { 452 ERROR_0("Microcode: channel 14 timeout\n"); 453 return -1; 454 } 455 456 DEBUG_0("Microcode: dsp_load: checkpoint 1\n"); 457 DEBUG("Microcode: TC_STATUS: %x\n", data); 458 459 /* transfer the code from program memory to data memory */ 460 RT_regw(VIP_TC_SOURCE, 0x00000000); 461 RT_regw(VIP_TC_DESTINATION, 0x10000000); 462 RT_regw(VIP_TC_COMMAND, 0xe0000006 | ((seg_list->num_bytes - 1) << 7)); 463 464 /* Wait until Shuttle bus channel 14 is available */ 465 i = data = 0; 466 RT_regr(VIP_TC_STATUS, &data); 467 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 468 RT_regr(VIP_TC_STATUS, &data); 469 470 if (i >= 10000) 471 { 472 ERROR_0("Microcode: channel 14 timeout\n"); 473 return -1; 474 } 475 DEBUG_0("Microcode: dsp_load: checkpoint 2\n"); 476 DEBUG("Microcode: TC_STATUS: %x\n", data); 477 478 /* Take DSP out from reset (0x0) */ 479 data = 0; 480 RT_regr(VIP_TC_DOWNLOAD, &data); 481 RT_regw(VIP_TC_DOWNLOAD, data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE); 482 483 RT_regr(VIP_TC_STATUS, &data); 484 DEBUG_0("Microcode: dsp_load: checkpoint 3\n"); 485 DEBUG("Microcode: TC_STATUS: %x\n", data); 486 487 /* send dsp_download_check_CRC */ 488 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); 489 fb_scratch1 = (unsigned int)seg_list->crc_val; 490 491 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 492 493 DEBUG_0("Microcode: dsp_load: checkpoint 4\n"); 494 } 495 496 if (tries >= 10) 497 { 498 ERROR_0("Microcode: Download of boot degment failed\n"); 499 return -1; 500 } 501 502 DEBUG_0("Microcode: Download of boot code succeeded\n"); 503 504 while((seg_list = seg_list->next) != NULL) 505 { 506 seg_id++; 507 result = tries = 0; 508 while(result != DSP_OK && tries < 10) 509 { 510 /* 511 * Configure shuttle bus for tranfer between DSP I/O "Program Interface" 512 * and Data Memory at address 0 513 */ 514 515 RT_regw(VIP_TC_SOURCE, 0x90000000); 516 RT_regw(VIP_TC_DESTINATION, 0x10000000); 517 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); 518 519 if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) 520 { 521 ERROR_0("Microcode: write to FIFOD failed\n"); 522 return -1; 523 } 524 525 i = data = 0; 526 RT_regr(VIP_TC_STATUS, &data); 527 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 528 RT_regr(VIP_TC_STATUS, &data); 529 530 /* send dsp_download_check_CRC */ 531 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); 532 fb_scratch1 = (unsigned int)seg_list->crc_val; 533 534 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 535 } 536 537 if (i >=10) 538 { 539 ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); 540 return -1; 541 } 542 543 DEBUG("Microcode: segment: %x loaded\n", seg_id); 544 545 /* 546 * The segment is downloaded correctly to data memory. Now move it to code memory 547 * by using dsp_download_code_transfer command. 548 */ 549 550 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 194); 551 fb_scratch1 = (unsigned int)seg_list->download_dst; 552 553 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 554 555 if (result != DSP_OK) 556 { 557 ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); 558 return -1; 559 } 560 } 561 562 DEBUG_0("Microcode: download complete\n"); 563 564 /* 565 * The last step is sending dsp_download_check_CRC with "download complete" 566 */ 567 568 fb_scratch0 = ((165 << 8) & 0xff00) | (0xff & 193); 569 fb_scratch1 = (unsigned int)0x11111; 570 571 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 572 573 if (result == DSP_OK) 574 DEBUG_0("Microcode: DSP microcode successfully loaded\n"); 575 else 576 { 577 ERROR_0("Microcode: DSP microcode UNsuccessfully loaded\n"); 578 return -1; 579 } 580 581 return 0; 582} 583 584static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) 585{ 586 uint32_t data; 587 int i; 588 589 /* 590 * Clear the FB_INT0 bit in INT_CNTL 591 */ 592 RT_regr(VIP_INT_CNTL, &data); 593 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); 594 595 /* 596 * Write FB_SCRATCHx registers. If FB_SCRATCH1==0 then we have a DWORD command. 597 */ 598 RT_regw(VIP_FB_SCRATCH0, fb_scratch0); 599 if (fb_scratch1 != 0) 600 RT_regw(VIP_FB_SCRATCH1, fb_scratch1); 601 602 /* 603 * Attention DSP. We are talking to you. 604 */ 605 RT_regr(VIP_FB_INT, &data); 606 RT_regw(VIP_FB_INT, data | VIP_FB_INT__INT_7); 607 608 /* 609 * Wait (by polling) for the DSP to process the command. 610 */ 611 i = 0; 612 RT_regr(VIP_INT_CNTL, &data); 613 while((!(data & VIP_INT_CNTL__FB_INT0)) /*&& (i++ < 10000)*/) 614 RT_regr(VIP_INT_CNTL, &data); 615 616 /* 617 * The return code is in FB_SCRATCH0 618 */ 619 RT_regr(VIP_FB_SCRATCH0, &fb_scratch0); 620 621 /* 622 * If we are here it means we got an answer. Clear the FB_INT0 bit. 623 */ 624 RT_regr(VIP_INT_CNTL, &data); 625 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); 626 627 628 return fb_scratch0; 629} 630 631static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) 632{ 633 uint32_t fb_scratch0 = 0; 634 uint32_t result; 635 int screen = t->VIP->pScrn->scrnIndex; 636 637 fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); 638 639 result = dsp_send_command(t, 0, fb_scratch0); 640 641 DEBUG_2("dsp_set_video_input_connector: %x, result: %x\n", connector, result); 642 643 return result; 644} 645 646#if 0 647static uint32_t dsp_reset(TheatrePtr t) 648{ 649 uint32_t fb_scratch0 = 0; 650 uint32_t result; 651 int screen = t->VIP->pScrn->scrnIndex; 652 653 fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); 654 655 result = dsp_send_command(t, 0, fb_scratch0); 656 657 DEBUG("dsp_reset: %x\n", result); 658 659 return result; 660} 661#endif 662 663static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) 664{ 665 uint32_t fb_scratch0 = 0; 666 uint32_t result; 667 int screen = t->VIP->pScrn->scrnIndex; 668 669 fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); 670 671 result = dsp_send_command(t, 0, fb_scratch0); 672 673 DEBUG("dsp_set_lowpowerstate: %x\n", result); 674 675 return result; 676} 677static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) 678{ 679 uint32_t fb_scratch0 = 0; 680 uint32_t result; 681 int screen = t->VIP->pScrn->scrnIndex; 682 683 fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); 684 685 result = dsp_send_command(t, 0, fb_scratch0); 686 687 DEBUG("dsp_set_video_standard: %x\n", result); 688 689 return result; 690} 691 692static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) 693{ 694 uint32_t fb_scratch0 = 0; 695 uint32_t result; 696 int screen = t->VIP->pScrn->scrnIndex; 697 698 fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); 699 700 result = dsp_send_command(t, 0, fb_scratch0); 701 702 DEBUG("dsp_set_videostreamformat: %x\n", result); 703 704 return result; 705} 706 707static uint32_t dsp_video_standard_detection(TheatrePtr t) 708{ 709 uint32_t fb_scratch0 = 0; 710 uint32_t result; 711 int screen = t->VIP->pScrn->scrnIndex; 712 713 fb_scratch0 = 0 | (54 & 0xff); 714 715 result = dsp_send_command(t, 0, fb_scratch0); 716 717 DEBUG("dsp_video_standard_detection: %x\n", result); 718 719 return result; 720} 721 722#if 0 723static uint32_t dsp_get_signallockstatus(TheatrePtr t) 724{ 725 uint32_t fb_scratch1 = 0; 726 uint32_t fb_scratch0 = 0; 727 uint32_t result; 728 int screen = t->VIP->pScrn->scrnIndex; 729 730 fb_scratch0 = 0 | (77 & 0xff); 731 732 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 733 734 DEBUG_3("dsp_get_signallockstatus: %x, h_pll: %x, v_pll: %x\n", \ 735 result, (result >> 8) & 0xff, (result >> 16) & 0xff); 736 737 return result; 738} 739 740static uint32_t dsp_get_signallinenumber(TheatrePtr t) 741{ 742 uint32_t fb_scratch1 = 0; 743 uint32_t fb_scratch0 = 0; 744 uint32_t result; 745 int screen = t->VIP->pScrn->scrnIndex; 746 747 fb_scratch0 = 0 | (78 & 0xff); 748 749 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 750 751 DEBUG_2("dsp_get_signallinenumber: %x, linenum: %x\n", \ 752 result, (result >> 8) & 0xffff); 753 754 return result; 755} 756#endif 757 758static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) 759{ 760 uint32_t fb_scratch1 = 0; 761 uint32_t fb_scratch0 = 0; 762 uint32_t result; 763 int screen = t->VIP->pScrn->scrnIndex; 764 765 fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); 766 767 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 768 769 DEBUG("dsp_set_brightness: %x\n", result); 770 771 return result; 772} 773 774static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) 775{ 776 uint32_t fb_scratch1 = 0; 777 uint32_t fb_scratch0 = 0; 778 uint32_t result; 779 int screen = t->VIP->pScrn->scrnIndex; 780 781 fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); 782 783 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 784 785 DEBUG("dsp_set_contrast: %x\n", result); 786 787 return result; 788} 789 790#if 0 791static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) 792{ 793 uint32_t fb_scratch1 = 0; 794 uint32_t fb_scratch0 = 0; 795 uint32_t result; 796 int screen = t->VIP->pScrn->scrnIndex; 797 798 fb_scratch0 = 0 | (73 & 0xff); 799 800 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 801 802 DEBUG("dsp_set_sharpness: %x\n", result); 803 804 return result; 805} 806#endif 807 808static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) 809{ 810 uint32_t fb_scratch1 = 0; 811 uint32_t fb_scratch0 = 0; 812 uint32_t result; 813 int screen = t->VIP->pScrn->scrnIndex; 814 815 fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); 816 817 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 818 819 DEBUG("dsp_set_tint: %x\n", result); 820 821 return result; 822} 823 824static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) 825{ 826 uint32_t fb_scratch1 = 0; 827 uint32_t fb_scratch0 = 0; 828 uint32_t result; 829 int screen = t->VIP->pScrn->scrnIndex; 830 831 fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); 832 833 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 834 835 DEBUG("dsp_set_saturation: %x\n", result); 836 837 return result; 838} 839 840static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) 841{ 842 uint32_t fb_scratch1 = 0; 843 uint32_t fb_scratch0 = 0; 844 uint32_t result; 845 int screen = t->VIP->pScrn->scrnIndex; 846 847 fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); 848 fb_scratch1 = ((horz_end << 16) & 0xffff0000) | (horz_start & 0xffff); 849 850 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 851 852 DEBUG("dsp_set_video_scaler_horizontal: %x\n", result); 853 854 return result; 855} 856 857static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) 858{ 859 uint32_t fb_scratch1 = 0; 860 uint32_t fb_scratch0 = 0; 861 uint32_t result; 862 int screen = t->VIP->pScrn->scrnIndex; 863 864 fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); 865 fb_scratch1 = ((vert_end << 16) & 0xffff0000) | (vert_start & 0xffff); 866 867 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 868 869 DEBUG("dsp_set_video_scaler_vertical: %x\n", result); 870 871 return result; 872} 873 874static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) 875{ 876 uint32_t fb_scratch1 = 0; 877 uint32_t fb_scratch0 = 0; 878 uint32_t result; 879 int screen = t->VIP->pScrn->scrnIndex; 880 881 fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); 882 883 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 884 885 DEBUG("dsp_audio_mute: %x\n", result); 886 887 return result; 888} 889 890static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) 891{ 892 uint32_t fb_scratch1 = 0; 893 uint32_t fb_scratch0 = 0; 894 uint32_t result; 895 int screen = t->VIP->pScrn->scrnIndex; 896 897 fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); 898 899 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 900 901 DEBUG("dsp_set_audio_volume: %x\n", result); 902 903 return result; 904} 905 906#if 0 907static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) 908{ 909 uint32_t fb_scratch1 = 0; 910 uint32_t fb_scratch0 = 0; 911 uint32_t result; 912 int screen = t->VIP->pScrn->scrnIndex; 913 914 fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); 915 916 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 917 918 DEBUG("dsp_audio_detection: %x\n", result); 919 920 return result; 921} 922#endif 923 924static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) 925{ 926 uint32_t fb_scratch1 = 0; 927 uint32_t fb_scratch0 = 0; 928 uint32_t result; 929 int screen = t->VIP->pScrn->scrnIndex; 930 931 fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); 932 933 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 934 935 DEBUG("dsp_configure_i2s_port: %x\n", result); 936 937 return result; 938} 939 940static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) 941{ 942 uint32_t fb_scratch1 = 0; 943 uint32_t fb_scratch0 = 0; 944 uint32_t result; 945 int screen = t->VIP->pScrn->scrnIndex; 946 947 fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); 948 949 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 950 951 DEBUG("dsp_configure_spdif_port: %x\n", result); 952 953 return result; 954} 955 956enum 957{ 958fld_tmpReg1=0, 959fld_tmpReg2, 960fld_tmpReg3, 961fld_LP_CONTRAST, 962fld_LP_BRIGHTNESS, 963fld_CP_HUE_CNTL, 964fld_LUMA_FILTER, 965fld_H_SCALE_RATIO, 966fld_H_SHARPNESS, 967fld_V_SCALE_RATIO, 968fld_V_DEINTERLACE_ON, 969fld_V_BYPSS, 970fld_V_DITHER_ON, 971fld_EVENF_OFFSET, 972fld_ODDF_OFFSET, 973fld_INTERLACE_DETECTED, 974fld_VS_LINE_COUNT, 975fld_VS_DETECTED_LINES, 976fld_VS_ITU656_VB, 977fld_VBI_CC_DATA, 978fld_VBI_CC_WT, 979fld_VBI_CC_WT_ACK, 980fld_VBI_CC_HOLD, 981fld_VBI_DECODE_EN, 982fld_VBI_CC_DTO_P, 983fld_VBI_20BIT_DTO_P, 984fld_VBI_CC_LEVEL, 985fld_VBI_20BIT_LEVEL, 986fld_VBI_CLK_RUNIN_GAIN, 987fld_H_VBI_WIND_START, 988fld_H_VBI_WIND_END, 989fld_V_VBI_WIND_START, 990fld_V_VBI_WIND_END, 991fld_VBI_20BIT_DATA0, 992fld_VBI_20BIT_DATA1, 993fld_VBI_20BIT_WT, 994fld_VBI_20BIT_WT_ACK, 995fld_VBI_20BIT_HOLD, 996fld_VBI_CAPTURE_ENABLE, 997fld_VBI_EDS_DATA, 998fld_VBI_EDS_WT, 999fld_VBI_EDS_WT_ACK, 1000fld_VBI_EDS_HOLD, 1001fld_VBI_SCALING_RATIO, 1002fld_VBI_ALIGNER_ENABLE, 1003fld_H_ACTIVE_START, 1004fld_H_ACTIVE_END, 1005fld_V_ACTIVE_START, 1006fld_V_ACTIVE_END, 1007fld_CH_HEIGHT, 1008fld_CH_KILL_LEVEL, 1009fld_CH_AGC_ERROR_LIM, 1010fld_CH_AGC_FILTER_EN, 1011fld_CH_AGC_LOOP_SPEED, 1012fld_HUE_ADJ, 1013fld_STANDARD_SEL, 1014fld_STANDARD_YC, 1015fld_ADC_PDWN, 1016fld_INPUT_SELECT, 1017fld_ADC_PREFLO, 1018fld_H_SYNC_PULSE_WIDTH, 1019fld_HS_GENLOCKED, 1020fld_HS_SYNC_IN_WIN, 1021fld_VIN_ASYNC_RST, 1022fld_DVS_ASYNC_RST, 1023fld_VIP_VENDOR_ID, 1024fld_VIP_DEVICE_ID, 1025fld_VIP_REVISION_ID, 1026fld_BLACK_INT_START, 1027fld_BLACK_INT_LENGTH, 1028fld_UV_INT_START, 1029fld_U_INT_LENGTH, 1030fld_V_INT_LENGTH, 1031fld_CRDR_ACTIVE_GAIN, 1032fld_CBDB_ACTIVE_GAIN, 1033fld_DVS_DIRECTION, 1034fld_DVS_VBI_UINT8_SWAP, 1035fld_DVS_CLK_SELECT, 1036fld_CONTINUOUS_STREAM, 1037fld_DVSOUT_CLK_DRV, 1038fld_DVSOUT_DATA_DRV, 1039fld_COMB_CNTL0, 1040fld_COMB_CNTL1, 1041fld_COMB_CNTL2, 1042fld_COMB_LENGTH, 1043fld_SYNCTIP_REF0, 1044fld_SYNCTIP_REF1, 1045fld_CLAMP_REF, 1046fld_AGC_PEAKWHITE, 1047fld_VBI_PEAKWHITE, 1048fld_WPA_THRESHOLD, 1049fld_WPA_TRIGGER_LO, 1050fld_WPA_TRIGGER_HIGH, 1051fld_LOCKOUT_START, 1052fld_LOCKOUT_END, 1053fld_CH_DTO_INC, 1054fld_PLL_SGAIN, 1055fld_PLL_FGAIN, 1056fld_CR_BURST_GAIN, 1057fld_CB_BURST_GAIN, 1058fld_VERT_LOCKOUT_START, 1059fld_VERT_LOCKOUT_END, 1060fld_H_IN_WIND_START, 1061fld_V_IN_WIND_START, 1062fld_H_OUT_WIND_WIDTH, 1063fld_V_OUT_WIND_WIDTH, 1064fld_HS_LINE_TOTAL, 1065fld_MIN_PULSE_WIDTH, 1066fld_MAX_PULSE_WIDTH, 1067fld_WIN_CLOSE_LIMIT, 1068fld_WIN_OPEN_LIMIT, 1069fld_VSYNC_INT_TRIGGER, 1070fld_VSYNC_INT_HOLD, 1071fld_VIN_M0, 1072fld_VIN_N0, 1073fld_MNFLIP_EN, 1074fld_VIN_P, 1075fld_REG_CLK_SEL, 1076fld_VIN_M1, 1077fld_VIN_N1, 1078fld_VIN_DRIVER_SEL, 1079fld_VIN_MNFLIP_REQ, 1080fld_VIN_MNFLIP_DONE, 1081fld_TV_LOCK_TO_VIN, 1082fld_TV_P_FOR_WINCLK, 1083fld_VINRST, 1084fld_VIN_CLK_SEL, 1085fld_VS_FIELD_BLANK_START, 1086fld_VS_FIELD_BLANK_END, 1087fld_VS_FIELD_IDLOCATION, 1088fld_VS_FRAME_TOTAL, 1089fld_SYNC_TIP_START, 1090fld_SYNC_TIP_LENGTH, 1091fld_GAIN_FORCE_DATA, 1092fld_GAIN_FORCE_EN, 1093fld_I_CLAMP_SEL, 1094fld_I_AGC_SEL, 1095fld_EXT_CLAMP_CAP, 1096fld_EXT_AGC_CAP, 1097fld_DECI_DITHER_EN, 1098fld_ADC_PREFHI, 1099fld_ADC_CH_GAIN_SEL, 1100fld_HS_PLL_SGAIN, 1101fld_NREn, 1102fld_NRGainCntl, 1103fld_NRBWTresh, 1104fld_NRGCTresh, 1105fld_NRCoefDespeclMode, 1106fld_GPIO_5_OE, 1107fld_GPIO_6_OE, 1108fld_GPIO_5_OUT, 1109fld_GPIO_6_OUT, 1110 1111regRT_MAX_REGS 1112} a; 1113 1114 1115typedef struct { 1116 uint8_t size; 1117 uint32_t fld_id; 1118 uint32_t dwRegAddrLSBs; 1119 uint32_t dwFldOffsetLSBs; 1120 uint32_t dwMaskLSBs; 1121 uint32_t addr2; 1122 uint32_t offs2; 1123 uint32_t mask2; 1124 uint32_t dwCurrValue; 1125 uint32_t rw; 1126 } RTREGMAP; 1127 1128#define READONLY 1 1129#define WRITEONLY 2 1130#define READWRITE 3 1131 1132/* Rage Theatre's Register Mappings, including the default values: */ 1133RTREGMAP RT_RegMap[regRT_MAX_REGS]={ 1134/* 1135{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W 1136*/ 1137{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE }, 1138{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 1139{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 1140{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE }, 1141{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE }, 1142{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE }, 1143{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE }, 1144{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE }, 1145{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE }, 1146{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE }, 1147{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE }, 1148{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE }, 1149{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE }, 1150{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE }, 1151{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE }, 1152{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY }, 1153{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY }, 1154{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY }, 1155{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY }, 1156{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE }, 1157{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE }, 1158{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY }, 1159{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE }, 1160{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE }, 1161{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE }, 1162{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE }, 1163{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE }, 1164{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE }, 1165{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE }, 1166{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE }, 1167{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE }, 1168{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE }, 1169{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */ 1170{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE }, 1171{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE }, 1172{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE }, 1173{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY }, 1174{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE }, 1175{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE }, 1176{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE }, 1177{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE }, 1178{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY }, 1179{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE }, 1180{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE }, 1181{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE }, 1182{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE }, 1183{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE }, 1184{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE }, 1185{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE }, 1186{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE }, 1187{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE }, 1188{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE }, 1189{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE }, 1190{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE }, 1191{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE }, 1192{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE }, 1193{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE }, 1194{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE }, 1195{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE }, 1196{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE }, 1197{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY }, 1198{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY }, 1199{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY }, 1200{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE }, 1201{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE }, 1202{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY }, 1203{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY }, 1204{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY }, 1205{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE }, 1206{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE }, 1207{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE }, 1208{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE }, 1209{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE }, 1210{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, 1211{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, 1212{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, 1213{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, 1214{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, 1215{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, 1216{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, 1217{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE }, 1218{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE }, 1219{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE }, 1220{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE }, 1221{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE }, 1222{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE }, 1223{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE }, 1224{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE }, 1225{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE }, 1226{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE }, 1227{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE }, 1228{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE }, 1229{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE }, 1230{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE }, 1231{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE }, 1232{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE }, 1233{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE }, 1234{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE }, 1235{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE }, 1236{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE }, 1237{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE }, 1238{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE }, 1239{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE }, 1240{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE }, 1241{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE }, 1242{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE }, 1243{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE }, 1244{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE }, 1245{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE }, 1246{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE }, 1247{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE }, 1248{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE }, 1249{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE }, 1250{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE }, 1251{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE }, 1252{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE }, 1253{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE }, 1254{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE }, 1255{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE }, 1256{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE }, 1257{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE }, 1258{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE }, 1259{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY }, 1260{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE }, 1261{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE }, 1262{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE }, 1263{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE }, 1264{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE }, 1265{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE }, 1266{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE }, 1267{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE }, 1268{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE }, 1269{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE }, 1270{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE }, 1271{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE }, 1272{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE }, 1273{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE }, 1274{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE }, 1275{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE }, 1276{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE }, 1277{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE }, 1278{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE }, 1279{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE }, 1280{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE }, 1281{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE }, 1282{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE }, 1283{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE }, 1284{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE }, 1285{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE }, 1286{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE }, 1287{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE }, 1288{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE }, 1289}; 1290 1291/* Rage Theatre's register fields default values: */ 1292uint32_t RT_RegDef[regRT_MAX_REGS]= 1293{ 1294fld_tmpReg1_def, 1295fld_tmpReg2_def, 1296fld_tmpReg3_def, 1297fld_LP_CONTRAST_def, 1298fld_LP_BRIGHTNESS_def, 1299fld_CP_HUE_CNTL_def, 1300fld_LUMA_FILTER_def, 1301fld_H_SCALE_RATIO_def, 1302fld_H_SHARPNESS_def, 1303fld_V_SCALE_RATIO_def, 1304fld_V_DEINTERLACE_ON_def, 1305fld_V_BYPSS_def, 1306fld_V_DITHER_ON_def, 1307fld_EVENF_OFFSET_def, 1308fld_ODDF_OFFSET_def, 1309fld_INTERLACE_DETECTED_def, 1310fld_VS_LINE_COUNT_def, 1311fld_VS_DETECTED_LINES_def, 1312fld_VS_ITU656_VB_def, 1313fld_VBI_CC_DATA_def, 1314fld_VBI_CC_WT_def, 1315fld_VBI_CC_WT_ACK_def, 1316fld_VBI_CC_HOLD_def, 1317fld_VBI_DECODE_EN_def, 1318fld_VBI_CC_DTO_P_def, 1319fld_VBI_20BIT_DTO_P_def, 1320fld_VBI_CC_LEVEL_def, 1321fld_VBI_20BIT_LEVEL_def, 1322fld_VBI_CLK_RUNIN_GAIN_def, 1323fld_H_VBI_WIND_START_def, 1324fld_H_VBI_WIND_END_def, 1325fld_V_VBI_WIND_START_def, 1326fld_V_VBI_WIND_END_def, 1327fld_VBI_20BIT_DATA0_def, 1328fld_VBI_20BIT_DATA1_def, 1329fld_VBI_20BIT_WT_def, 1330fld_VBI_20BIT_WT_ACK_def, 1331fld_VBI_20BIT_HOLD_def, 1332fld_VBI_CAPTURE_ENABLE_def, 1333fld_VBI_EDS_DATA_def, 1334fld_VBI_EDS_WT_def, 1335fld_VBI_EDS_WT_ACK_def, 1336fld_VBI_EDS_HOLD_def, 1337fld_VBI_SCALING_RATIO_def, 1338fld_VBI_ALIGNER_ENABLE_def, 1339fld_H_ACTIVE_START_def, 1340fld_H_ACTIVE_END_def, 1341fld_V_ACTIVE_START_def, 1342fld_V_ACTIVE_END_def, 1343fld_CH_HEIGHT_def, 1344fld_CH_KILL_LEVEL_def, 1345fld_CH_AGC_ERROR_LIM_def, 1346fld_CH_AGC_FILTER_EN_def, 1347fld_CH_AGC_LOOP_SPEED_def, 1348fld_HUE_ADJ_def, 1349fld_STANDARD_SEL_def, 1350fld_STANDARD_YC_def, 1351fld_ADC_PDWN_def, 1352fld_INPUT_SELECT_def, 1353fld_ADC_PREFLO_def, 1354fld_H_SYNC_PULSE_WIDTH_def, 1355fld_HS_GENLOCKED_def, 1356fld_HS_SYNC_IN_WIN_def, 1357fld_VIN_ASYNC_RST_def, 1358fld_DVS_ASYNC_RST_def, 1359fld_VIP_VENDOR_ID_def, 1360fld_VIP_DEVICE_ID_def, 1361fld_VIP_REVISION_ID_def, 1362fld_BLACK_INT_START_def, 1363fld_BLACK_INT_LENGTH_def, 1364fld_UV_INT_START_def, 1365fld_U_INT_LENGTH_def, 1366fld_V_INT_LENGTH_def, 1367fld_CRDR_ACTIVE_GAIN_def, 1368fld_CBDB_ACTIVE_GAIN_def, 1369fld_DVS_DIRECTION_def, 1370fld_DVS_VBI_UINT8_SWAP_def, 1371fld_DVS_CLK_SELECT_def, 1372fld_CONTINUOUS_STREAM_def, 1373fld_DVSOUT_CLK_DRV_def, 1374fld_DVSOUT_DATA_DRV_def, 1375fld_COMB_CNTL0_def, 1376fld_COMB_CNTL1_def, 1377fld_COMB_CNTL2_def, 1378fld_COMB_LENGTH_def, 1379fld_SYNCTIP_REF0_def, 1380fld_SYNCTIP_REF1_def, 1381fld_CLAMP_REF_def, 1382fld_AGC_PEAKWHITE_def, 1383fld_VBI_PEAKWHITE_def, 1384fld_WPA_THRESHOLD_def, 1385fld_WPA_TRIGGER_LO_def, 1386fld_WPA_TRIGGER_HIGH_def, 1387fld_LOCKOUT_START_def, 1388fld_LOCKOUT_END_def, 1389fld_CH_DTO_INC_def, 1390fld_PLL_SGAIN_def, 1391fld_PLL_FGAIN_def, 1392fld_CR_BURST_GAIN_def, 1393fld_CB_BURST_GAIN_def, 1394fld_VERT_LOCKOUT_START_def, 1395fld_VERT_LOCKOUT_END_def, 1396fld_H_IN_WIND_START_def, 1397fld_V_IN_WIND_START_def, 1398fld_H_OUT_WIND_WIDTH_def, 1399fld_V_OUT_WIND_WIDTH_def, 1400fld_HS_LINE_TOTAL_def, 1401fld_MIN_PULSE_WIDTH_def, 1402fld_MAX_PULSE_WIDTH_def, 1403fld_WIN_CLOSE_LIMIT_def, 1404fld_WIN_OPEN_LIMIT_def, 1405fld_VSYNC_INT_TRIGGER_def, 1406fld_VSYNC_INT_HOLD_def, 1407fld_VIN_M0_def, 1408fld_VIN_N0_def, 1409fld_MNFLIP_EN_def, 1410fld_VIN_P_def, 1411fld_REG_CLK_SEL_def, 1412fld_VIN_M1_def, 1413fld_VIN_N1_def, 1414fld_VIN_DRIVER_SEL_def, 1415fld_VIN_MNFLIP_REQ_def, 1416fld_VIN_MNFLIP_DONE_def, 1417fld_TV_LOCK_TO_VIN_def, 1418fld_TV_P_FOR_WINCLK_def, 1419fld_VINRST_def, 1420fld_VIN_CLK_SEL_def, 1421fld_VS_FIELD_BLANK_START_def, 1422fld_VS_FIELD_BLANK_END_def, 1423fld_VS_FIELD_IDLOCATION_def, 1424fld_VS_FRAME_TOTAL_def, 1425fld_SYNC_TIP_START_def, 1426fld_SYNC_TIP_LENGTH_def, 1427fld_GAIN_FORCE_DATA_def, 1428fld_GAIN_FORCE_EN_def, 1429fld_I_CLAMP_SEL_def, 1430fld_I_AGC_SEL_def, 1431fld_EXT_CLAMP_CAP_def, 1432fld_EXT_AGC_CAP_def, 1433fld_DECI_DITHER_EN_def, 1434fld_ADC_PREFHI_def, 1435fld_ADC_CH_GAIN_SEL_def, 1436fld_HS_PLL_SGAIN_def, 1437fld_NREn_def, 1438fld_NRGainCntl_def, 1439fld_NRBWTresh_def, 1440fld_NRGCTresh_def, 1441fld_NRCoefDespeclMode_def, 1442fld_GPIO_5_OE_def, 1443fld_GPIO_6_OE_def, 1444fld_GPIO_5_OUT_def, 1445fld_GPIO_6_OUT_def, 1446}; 1447 1448/**************************************************************************** 1449 * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * 1450 * Function: Writes a register field within Rage Theatre * 1451 * Inputs: uint32_t dwReg = register field to be written * 1452 * uint32_t dwData = data that will be written to the reg field * 1453 * Outputs: NONE * 1454 ****************************************************************************/ 1455static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) 1456{ 1457 uint32_t dwResult=0; 1458 uint32_t dwValue=0; 1459 1460 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 1461 { 1462 dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) | 1463 (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs); 1464 1465 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE) 1466 { 1467 /* update the memory mapped registers */ 1468 RT_RegMap[dwReg].dwCurrValue = dwData; 1469 } 1470 } 1471 1472 return; 1473 1474} /* WriteRT_fld ()... */ 1475 1476#if 0 1477/**************************************************************************** 1478 * ReadRT_fld (uint32_t dwReg) * 1479 * Function: Reads a register field within Rage Theatre * 1480 * Inputs: uint32_t dwReg = register field to be read * 1481 * Outputs: uint32_t - value read from register field * 1482 ****************************************************************************/ 1483static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) 1484{ 1485 uint32_t dwResult=0; 1486 1487 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 1488 { 1489 RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >> 1490 RT_RegMap[dwReg].dwFldOffsetLSBs); 1491 return (RT_RegMap[dwReg].dwCurrValue); 1492 } 1493 else 1494 { 1495 return (0xFFFFFFFF); 1496 } 1497 1498} /* ReadRT_fld ()... */ 1499 1500#define ReadRT_fld(a) ReadRT_fld1(t,(a)) 1501#endif 1502 1503#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b)) 1504 1505 1506/**************************************************************************** 1507 * RT_SetTint (int hue) * 1508 * Function: sets the tint (hue) for the Rage Theatre video in * 1509 * Inputs: int hue - the hue value to be set. * 1510 * Outputs: NONE * 1511 ****************************************************************************/ 1512_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) 1513{ 1514 /* Validate Hue level */ 1515 if (hue < -1000) 1516 { 1517 hue = -1000; 1518 } 1519 else if (hue > 1000) 1520 { 1521 hue = 1000; 1522 } 1523 1524 t->iHue=hue; 1525 1526 dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); 1527 1528} /* RT_SetTint ()... */ 1529 1530 1531/**************************************************************************** 1532 * RT_SetSaturation (int Saturation) * 1533 * Function: sets the saturation level for the Rage Theatre video in * 1534 * Inputs: int Saturation - the saturation value to be set. * 1535 * Outputs: NONE * 1536 ****************************************************************************/ 1537_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) 1538{ 1539 /* VALIDATE SATURATION LEVEL */ 1540 if (Saturation < -1000L) 1541 { 1542 Saturation = -1000; 1543 } 1544 else if (Saturation > 1000L) 1545 { 1546 Saturation = 1000; 1547 } 1548 1549 t->iSaturation = Saturation; 1550 1551 /* RT200 has saturation in range 0 to 255 with nominal value 128 */ 1552 dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); 1553 1554 return; 1555} /* RT_SetSaturation ()...*/ 1556 1557/**************************************************************************** 1558 * RT_SetBrightness (int Brightness) * 1559 * Function: sets the brightness level for the Rage Theatre video in * 1560 * Inputs: int Brightness - the brightness value to be set. * 1561 * Outputs: NONE * 1562 ****************************************************************************/ 1563_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) 1564{ 1565 /* VALIDATE BRIGHTNESS LEVEL */ 1566 if (Brightness < -1000) 1567 { 1568 Brightness = -1000; 1569 } 1570 else if (Brightness > 1000) 1571 { 1572 Brightness = 1000; 1573 } 1574 1575 /* Save value */ 1576 t->iBrightness = Brightness; 1577 t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; 1578 1579 /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ 1580 dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); 1581 1582 return; 1583} /* RT_SetBrightness ()... */ 1584 1585 1586/**************************************************************************** 1587 * RT_SetSharpness (uint16_t wSharpness) * 1588 * Function: sets the sharpness level for the Rage Theatre video in * 1589 * Inputs: uint16_t wSharpness - the sharpness value to be set. * 1590 * Outputs: NONE * 1591 ****************************************************************************/ 1592_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) 1593{ 1594 switch (wSharpness) 1595 { 1596 case DEC_SMOOTH : 1597 WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS); 1598 t->wSharpness = RT_NORM_SHARPNESS; 1599 break; 1600 case DEC_SHARP : 1601 WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS); 1602 t->wSharpness = RT_HIGH_SHARPNESS; 1603 break; 1604 default: 1605 break; 1606 } 1607 return; 1608 1609} /* RT_SetSharpness ()... */ 1610 1611 1612/**************************************************************************** 1613 * RT_SetContrast (int Contrast) * 1614 * Function: sets the contrast level for the Rage Theatre video in * 1615 * Inputs: int Contrast - the contrast value to be set. * 1616 * Outputs: NONE * 1617 ****************************************************************************/ 1618_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) 1619{ 1620 /* VALIDATE CONTRAST LEVEL */ 1621 if (Contrast < -1000) 1622 { 1623 Contrast = -1000; 1624 } 1625 else if (Contrast > 1000) 1626 { 1627 Contrast = 1000; 1628 } 1629 1630 /* Save contrast value */ 1631 t->iContrast = Contrast; 1632 t->dbContrast = (double) (Contrast+1000.0) / 1000.0; 1633 1634 /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ 1635 dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); 1636 return; 1637 1638} /* RT_SetContrast ()... */ 1639 1640/**************************************************************************** 1641 * RT_SetInterlace (uint8_t bInterlace) * 1642 * Function: to set the interlacing pattern for the Rage Theatre video in * 1643 * Inputs: uint8_t bInterlace * 1644 * Outputs: NONE * 1645 ****************************************************************************/ 1646_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) 1647{ 1648 switch(bInterlace) 1649 { 1650 case (TRUE): /*DEC_INTERLACE */ 1651 WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); 1652 t->wInterlaced = (uint16_t) RT_DECINTERLACED; 1653 break; 1654 case (FALSE): /*DEC_NONINTERLACE */ 1655 WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); 1656 t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; 1657 break; 1658 default: 1659 break; 1660 } 1661 1662 return; 1663 1664} /* RT_SetInterlace ()... */ 1665 1666 1667/**************************************************************************** 1668 * RT_SetStandard (uint16_t wStandard) * 1669 * Function: to set the input standard for the Rage Theatre video in * 1670 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1671 * Outputs: NONE * 1672 ****************************************************************************/ 1673_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) 1674{ 1675 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", 1676 wStandard); 1677 1678 t->wStandard = wStandard; 1679 1680 /* Program the new standards: */ 1681 switch (wStandard & 0x00FF) 1682 { 1683 case (DEC_NTSC): /*NTSC GROUP - 480 lines */ 1684 switch (wStandard & 0xFF00) 1685 { 1686 case (extNONE): 1687 case (extNTSC): 1688 dsp_set_video_standard(t, 2); 1689 break; 1690 case (extNTSC_J): 1691 dsp_set_video_standard(t, RT200_NTSC_J); 1692 break; 1693 case (extNTSC_443): 1694 dsp_set_video_standard(t, RT200_NTSC_433); 1695 break; 1696 default: 1697 dsp_video_standard_detection(t); 1698 break; 1699 } 1700 break; 1701 case (DEC_PAL): /*PAL GROUP - 625 lines */ 1702 switch (wStandard & 0xFF00) 1703 { 1704 case (extNONE): 1705 case (extPAL): 1706 case (extPAL_B): 1707 case (extPAL_BGHI): 1708 dsp_set_video_standard(t, RT200_PAL_B); 1709 break; 1710 case (extPAL_D): 1711 dsp_set_video_standard(t, RT200_PAL_D); 1712 break; 1713 case (extPAL_G): 1714 dsp_set_video_standard(t, RT200_PAL_G); 1715 break; 1716 case (extPAL_H): 1717 dsp_set_video_standard(t, RT200_PAL_H); 1718 break; 1719 case (extPAL_I): 1720 dsp_set_video_standard(t, RT200_PAL_D); 1721 break; 1722 case (extPAL_N): 1723 dsp_set_video_standard(t, RT200_PAL_N); 1724 break; 1725 case (extPAL_NCOMB): 1726 dsp_set_video_standard(t, RT200_PAL_Ncomb); 1727 break; 1728 case (extPAL_M): 1729 dsp_set_video_standard(t, RT200_PAL_M); 1730 break; 1731 case (extPAL_60): 1732 dsp_set_video_standard(t, RT200_PAL_60); 1733 break; 1734 default: 1735 dsp_video_standard_detection(t); 1736 break; 1737 } 1738 break; 1739 case (DEC_SECAM): /*SECAM GROUP*/ 1740 switch (wStandard & 0xFF00) 1741 { 1742 case (extNONE): 1743 case (extSECAM): 1744 dsp_set_video_standard(t, RT200_SECAM); 1745 break; 1746 case (extSECAM_B): 1747 dsp_set_video_standard(t, RT200_SECAM_B); 1748 break; 1749 case (extSECAM_D): 1750 dsp_set_video_standard(t, RT200_SECAM_D); 1751 break; 1752 case (extSECAM_G): 1753 dsp_set_video_standard(t, RT200_SECAM_G); 1754 break; 1755 case (extSECAM_H): 1756 dsp_set_video_standard(t, RT200_SECAM_H); 1757 break; 1758 case (extSECAM_K): 1759 dsp_set_video_standard(t, RT200_SECAM_K); 1760 break; 1761 case (extSECAM_K1): 1762 dsp_set_video_standard(t, RT200_SECAM_K1); 1763 break; 1764 case (extSECAM_L): 1765 dsp_set_video_standard(t, RT200_SECAM_L); 1766 break; 1767 case (extSECAM_L1): 1768 dsp_set_video_standard(t, RT200_SECAM_L1); 1769 break; 1770 default: 1771 dsp_video_standard_detection(t); 1772 break; 1773 } 1774 break; 1775 default: 1776 dsp_video_standard_detection(t); 1777 } 1778 1779} /* RT_SetStandard ()... */ 1780 1781 1782/**************************************************************************** 1783 * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * 1784 * uint8_t fCC_On, uint8_t fVBICap_On) * 1785 * Function: sets the output video size for the Rage Theatre video in * 1786 * Inputs: uint16_t wHorzSize - width of output in pixels * 1787 * uint16_t wVertSize - height of output in pixels (lines) * 1788 * uint8_t fCC_On - enable CC output * 1789 * uint8_t fVBI_Cap_On - enable VBI capture * 1790 * Outputs: NONE * 1791 ****************************************************************************/ 1792_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) 1793{ 1794 /* VBI is ignored now */ 1795 1796 /* 1797 * If I pass the (wHorzSize, 0, 0) (wVertSize, 0, 0) the image does not synchronize 1798 */ 1799 dsp_set_video_scaler_horizontal(t, 0, 0, 0); 1800 dsp_set_video_scaler_vertical(t, 0, 0, 0); 1801 1802} /* RT_SetOutputVideoSize ()...*/ 1803 1804 1805/**************************************************************************** 1806 * RT_SetConnector (uint16_t wStandard, int tunerFlag) * 1807 * Function: 1808 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1809 * int tunerFlag 1810 * Outputs: NONE * 1811 ****************************************************************************/ 1812_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) 1813{ 1814 uint32_t data; 1815 1816 t->wConnector = wConnector; 1817 1818 theatre_read(t, VIP_GPIO_CNTL, &data); 1819 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", 1820 (unsigned)data); 1821 1822 theatre_read(t, VIP_GPIO_INOUT, &data); 1823 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", 1824 (unsigned)data); 1825 1826 switch (wConnector) 1827 { 1828 case (DEC_TUNER): /* Tuner*/ 1829 /* RT200 does not have any input connector 0 */ 1830 dsp_set_video_input_connector(t, t->wTunerConnector + 1); 1831 1832 /* this is to set the analog mux used for sond */ 1833 theatre_read(t, VIP_GPIO_CNTL, &data); 1834 data &= ~0x10; 1835 theatre_write(t, VIP_GPIO_CNTL, data); 1836 1837 theatre_read(t, VIP_GPIO_INOUT, &data); 1838 data &= ~0x10; 1839 theatre_write(t, VIP_GPIO_INOUT, data); 1840 1841 break; 1842 case (DEC_COMPOSITE): /* Comp*/ 1843 dsp_set_video_input_connector(t, t->wComp0Connector); 1844 1845 /* this is to set the analog mux used for sond */ 1846 theatre_read(t, VIP_GPIO_CNTL, &data); 1847 data |= 0x10; 1848 theatre_write(t, VIP_GPIO_CNTL, data); 1849 1850 theatre_read(t, VIP_GPIO_INOUT, &data); 1851 data |= 0x10; 1852 theatre_write(t, VIP_GPIO_INOUT, data); 1853 1854 break; 1855 case (DEC_SVIDEO): /* Svideo*/ 1856 dsp_set_video_input_connector(t, t->wSVideo0Connector); 1857 1858 /* this is to set the analog mux used for sond */ 1859 theatre_read(t, VIP_GPIO_CNTL, &data); 1860 data |= 0x10; 1861 theatre_write(t, VIP_GPIO_CNTL, data); 1862 1863 theatre_read(t, VIP_GPIO_INOUT, &data); 1864 data |= 0x10; 1865 theatre_write(t, VIP_GPIO_INOUT, data); 1866 1867 break; 1868 default: 1869 dsp_set_video_input_connector(t, t->wComp0Connector); 1870 } 1871 1872 theatre_read(t, VIP_GPIO_CNTL, &data); 1873 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", 1874 (unsigned)data); 1875 1876 theatre_read(t, VIP_GPIO_INOUT, &data); 1877 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", 1878 (unsigned)data); 1879 1880 1881 dsp_configure_i2s_port(t, 0, 0, 0); 1882 dsp_configure_spdif_port(t, 0); 1883 1884 /*dsp_audio_detection(t, 0);*/ 1885 dsp_audio_mute(t, 1, 1); 1886 dsp_set_audio_volume(t, 128, 128, 0); 1887 1888} /* RT_SetConnector ()...*/ 1889 1890 1891_X_EXPORT void InitTheatre(TheatrePtr t) 1892{ 1893 uint32_t data; 1894 uint32_t M, N, P; 1895 1896 /* this will give 108Mhz at 27Mhz reference */ 1897 M = 28; 1898 N = 224; 1899 P = 1; 1900 1901 ShutdownTheatre(t); 1902 usleep(100000); 1903 t->mode=MODE_INITIALIZATION_IN_PROGRESS; 1904 1905 1906 data = M | (N << 11) | (P <<24); 1907 RT_regw(VIP_DSP_PLL_CNTL, data); 1908 1909 RT_regr(VIP_PLL_CNTL0, &data); 1910 data |= 0x2000; 1911 RT_regw(VIP_PLL_CNTL0, data); 1912 1913 /* RT_regw(VIP_I2C_SLVCNTL, 0x249); */ 1914 RT_regr(VIP_PLL_CNTL1, &data); 1915 data |= 0x00030003; 1916 RT_regw(VIP_PLL_CNTL1, data); 1917 1918 RT_regr(VIP_PLL_CNTL0, &data); 1919 data &= 0xfffffffc; 1920 RT_regw(VIP_PLL_CNTL0, data); 1921 usleep(15000); 1922 1923 RT_regr(VIP_CLOCK_SEL_CNTL, &data); 1924 data |= 0x1b; 1925 RT_regw(VIP_CLOCK_SEL_CNTL, data); 1926 1927 RT_regr(VIP_MASTER_CNTL, &data); 1928 data &= 0xffffff07; 1929 RT_regw(VIP_MASTER_CNTL, data); 1930 data &= 0xffffff03; 1931 RT_regw(VIP_MASTER_CNTL, data); 1932 usleep(1000); 1933 1934 if (t->microc_path == NULL) 1935 { 1936 t->microc_path = DEFAULT_MICROC_PATH; 1937 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use default microcode path: %s\n", DEFAULT_MICROC_PATH); 1938 } 1939 else 1940 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use microcode path: %s\n", t->microc_path); 1941 1942 1943 if (t->microc_type == NULL) 1944 { 1945 t->microc_type = DEFAULT_MICROC_TYPE; 1946 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use default microcode type: %s\n", DEFAULT_MICROC_TYPE); 1947 } 1948 else 1949 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: Use microcode type: %s\n", t->microc_type); 1950 1951 if (DownloadMicrocode(t) < 0) 1952 { 1953 ShutdownTheatre(t); 1954 return; 1955 } 1956 1957 dsp_set_lowpowerstate(t, 1); 1958 dsp_set_videostreamformat(t, 1); 1959 1960 t->mode=MODE_INITIALIZED_FOR_TV_IN; 1961} 1962 1963static int DownloadMicrocode(TheatrePtr t) 1964{ 1965 struct rt200_microc_data microc_data; 1966 microc_data.microc_seg_list = NULL; 1967 1968 if (microc_load(t->microc_path, t->microc_type, µc_data, t->VIP->pScrn->scrnIndex) < 0) 1969 { 1970 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: cannot load microcode\n"); 1971 goto err_exit; 1972 } 1973 else 1974 { 1975 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: device_id: %x\n", microc_data.microc_head.device_id); 1976 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: vendor_id: %x\n", microc_data.microc_head.vendor_id); 1977 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: rev_id: %x\n", microc_data.microc_head.revision_id); 1978 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: num_seg: %x\n", microc_data.microc_head.num_seg); 1979 } 1980 1981 if (dsp_init(t, µc_data) < 0) 1982 { 1983 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: dsp_init failed\n"); 1984 goto err_exit; 1985 } 1986 else 1987 { 1988 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: dsp_init OK\n"); 1989 } 1990 1991 if (dsp_load(t, µc_data) < 0) 1992 { 1993 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_ERROR, "Microcode: dsp_download failed\n"); 1994 goto err_exit; 1995 } 1996 else 1997 { 1998 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Microcode: dsp_download OK\n"); 1999 } 2000 2001 microc_clean(µc_data, t->VIP->pScrn->scrnIndex); 2002 return 0; 2003 2004err_exit: 2005 2006 microc_clean(µc_data, t->VIP->pScrn->scrnIndex); 2007 return -1; 2008 2009} 2010 2011 2012_X_EXPORT void ShutdownTheatre(TheatrePtr t) 2013{ 2014#if 0 2015 WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); 2016 WriteRT_fld (fld_VINRST , RT_VINRST_RESET); 2017 WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE); 2018 WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); 2019#endif 2020 t->mode=MODE_UNINITIALIZED; 2021} 2022 2023_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) 2024{ 2025 int i; 2026 uint32_t data; 2027 2028 for(i=0;i<0x900;i+=4) 2029 { 2030 RT_regr(i, &data); 2031 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 2032 "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); 2033 } 2034 2035} 2036 2037void DumpRageTheatreRegsByName(TheatrePtr t) 2038{ 2039 int i; 2040 uint32_t data; 2041 struct { char *name; long addr; } rt_reg_list[]={ 2042 { "ADC_CNTL ", 0x0400 }, 2043 { "ADC_DEBUG ", 0x0404 }, 2044 { "AUD_CLK_DIVIDERS ", 0x00e8 }, 2045 { "AUD_DTO_INCREMENTS ", 0x00ec }, 2046 { "AUD_PLL_CNTL ", 0x00e0 }, 2047 { "AUD_PLL_FINE_CNTL ", 0x00e4 }, 2048 { "CLKOUT_CNTL ", 0x004c }, 2049 { "CLKOUT_GPIO_CNTL ", 0x0038 }, 2050 { "CLOCK_SEL_CNTL ", 0x00d0 }, 2051 { "COMB_CNTL0 ", 0x0440 }, 2052 { "COMB_CNTL1 ", 0x0444 }, 2053 { "COMB_CNTL2 ", 0x0448 }, 2054 { "COMB_LINE_LENGTH ", 0x044c }, 2055 { "CP_ACTIVE_GAIN ", 0x0594 }, 2056 { "CP_AGC_CNTL ", 0x0590 }, 2057 { "CP_BURST_GAIN ", 0x058c }, 2058 { "CP_DEBUG_FORCE ", 0x05b8 }, 2059 { "CP_HUE_CNTL ", 0x0588 }, 2060 { "CP_PLL_CNTL0 ", 0x0580 }, 2061 { "CP_PLL_CNTL1 ", 0x0584 }, 2062 { "CP_PLL_STATUS0 ", 0x0598 }, 2063 { "CP_PLL_STATUS1 ", 0x059c }, 2064 { "CP_PLL_STATUS2 ", 0x05a0 }, 2065 { "CP_PLL_STATUS3 ", 0x05a4 }, 2066 { "CP_PLL_STATUS4 ", 0x05a8 }, 2067 { "CP_PLL_STATUS5 ", 0x05ac }, 2068 { "CP_PLL_STATUS6 ", 0x05b0 }, 2069 { "CP_PLL_STATUS7 ", 0x05b4 }, 2070 { "CP_VERT_LOCKOUT ", 0x05bc }, 2071 { "CRC_CNTL ", 0x02c0 }, 2072 { "CRT_DTO_INCREMENTS ", 0x0394 }, 2073 { "CRT_PLL_CNTL ", 0x00c4 }, 2074 { "CRT_PLL_FINE_CNTL ", 0x00bc }, 2075 { "DECODER_DEBUG_CNTL ", 0x05d4 }, 2076 { "DELAY_ONE_MAP_A ", 0x0114 }, 2077 { "DELAY_ONE_MAP_B ", 0x0118 }, 2078 { "DELAY_ZERO_MAP_A ", 0x011c }, 2079 { "DELAY_ZERO_MAP_B ", 0x0120 }, 2080 { "DFCOUNT ", 0x00a4 }, 2081 { "DFRESTART ", 0x00a8 }, 2082 { "DHRESTART ", 0x00ac }, 2083 { "DVRESTART ", 0x00b0 }, 2084 { "DVS_PORT_CTRL ", 0x0610 }, 2085 { "DVS_PORT_READBACK ", 0x0614 }, 2086 { "FIFOA_CONFIG ", 0x0800 }, 2087 { "FIFOB_CONFIG ", 0x0804 }, 2088 { "FIFOC_CONFIG ", 0x0808 }, 2089 { "FRAME_LOCK_CNTL ", 0x0100 }, 2090 { "GAIN_LIMIT_SETTINGS ", 0x01e4 }, 2091 { "GPIO_CNTL ", 0x0034 }, 2092 { "GPIO_INOUT ", 0x0030 }, 2093 { "HCOUNT ", 0x0090 }, 2094 { "HDISP ", 0x0084 }, 2095 { "HOST_RD_WT_CNTL ", 0x0188 }, 2096 { "HOST_READ_DATA ", 0x0180 }, 2097 { "HOST_WRITE_DATA ", 0x0184 }, 2098 { "HSIZE ", 0x0088 }, 2099 { "HSTART ", 0x008c }, 2100 { "HS_DTOINC ", 0x0484 }, 2101 { "HS_GENLOCKDELAY ", 0x0490 }, 2102 { "HS_MINMAXWIDTH ", 0x048c }, 2103 { "HS_PLINE ", 0x0480 }, 2104 { "HS_PLLGAIN ", 0x0488 }, 2105 { "HS_PLL_ERROR ", 0x04a0 }, 2106 { "HS_PLL_FS_PATH ", 0x04a4 }, 2107 { "HS_PULSE_WIDTH ", 0x049c }, 2108 { "HS_WINDOW_LIMIT ", 0x0494 }, 2109 { "HS_WINDOW_OC_SPEED ", 0x0498 }, 2110 { "HTOTAL ", 0x0080 }, 2111 { "HW_DEBUG ", 0x0010 }, 2112 { "H_ACTIVE_WINDOW ", 0x05c0 }, 2113 { "H_SCALER_CONTROL ", 0x0600 }, 2114 { "H_VBI_WINDOW ", 0x05c8 }, 2115 { "I2C_CNTL ", 0x0054 }, 2116 { "I2C_CNTL_0 ", 0x0020 }, 2117 { "I2C_CNTL_1 ", 0x0024 }, 2118 { "I2C_DATA ", 0x0028 }, 2119 { "I2S_RECEIVE_CNTL ", 0x081c }, 2120 { "I2S_TRANSMIT_CNTL ", 0x0818 }, 2121 { "IIS_TX_CNT_REG ", 0x0824 }, 2122 { "INT_CNTL ", 0x002c }, 2123 { "L54_DTO_INCREMENTS ", 0x00f8 }, 2124 { "L54_PLL_CNTL ", 0x00f0 }, 2125 { "L54_PLL_FINE_CNTL ", 0x00f4 }, 2126 { "LINEAR_GAIN_SETTINGS ", 0x01e8 }, 2127 { "LP_AGC_CLAMP_CNTL0 ", 0x0500 }, 2128 { "LP_AGC_CLAMP_CNTL1 ", 0x0504 }, 2129 { "LP_BLACK_LEVEL ", 0x051c }, 2130 { "LP_BRIGHTNESS ", 0x0508 }, 2131 { "LP_CONTRAST ", 0x050c }, 2132 { "LP_SLICE_LEVEL ", 0x0520 }, 2133 { "LP_SLICE_LIMIT ", 0x0510 }, 2134 { "LP_SYNCTIP_LEVEL ", 0x0524 }, 2135 { "LP_VERT_LOCKOUT ", 0x0528 }, 2136 { "LP_WPA_CNTL0 ", 0x0514 }, 2137 { "LP_WPA_CNTL1 ", 0x0518 }, 2138 { "MASTER_CNTL ", 0x0040 }, 2139 { "MODULATOR_CNTL1 ", 0x0200 }, 2140 { "MODULATOR_CNTL2 ", 0x0204 }, 2141 { "MV_LEVEL_CNTL1 ", 0x0210 }, 2142 { "MV_LEVEL_CNTL2 ", 0x0214 }, 2143 { "MV_MODE_CNTL ", 0x0208 }, 2144 { "MV_STATUS ", 0x0330 }, 2145 { "MV_STRIPE_CNTL ", 0x020c }, 2146 { "NOISE_CNTL0 ", 0x0450 }, 2147 { "PLL_CNTL0 ", 0x00c8 }, 2148 { "PLL_CNTL1 ", 0x00fc }, 2149 { "PLL_TEST_CNTL ", 0x00cc }, 2150 { "PRE_DAC_MUX_CNTL ", 0x0240 }, 2151 { "RGB_CNTL ", 0x0048 }, 2152 { "RIPINTF_PORT_CNTL ", 0x003c }, 2153 { "SCALER_IN_WINDOW ", 0x0618 }, 2154 { "SCALER_OUT_WINDOW ", 0x061c }, 2155 { "SG_BLACK_GATE ", 0x04c0 }, 2156 { "SG_SYNCTIP_GATE ", 0x04c4 }, 2157 { "SG_UVGATE_GATE ", 0x04c8 }, 2158 { "SINGLE_STEP_DATA ", 0x05d8 }, 2159 { "SPDIF_AC3_PREAMBLE ", 0x0814 }, 2160 { "SPDIF_CHANNEL_STAT ", 0x0810 }, 2161 { "SPDIF_PORT_CNTL ", 0x080c }, 2162 { "SPDIF_TX_CNT_REG ", 0x0820 }, 2163 { "STANDARD_SELECT ", 0x0408 }, 2164 { "SW_SCRATCH ", 0x0014 }, 2165 { "SYNC_CNTL ", 0x0050 }, 2166 { "SYNC_LOCK_CNTL ", 0x0104 }, 2167 { "SYNC_SIZE ", 0x00b4 }, 2168 { "THERMO2BIN_STATUS ", 0x040c }, 2169 { "TIMING_CNTL ", 0x01c4 }, 2170 { "TVO_DATA_DELAY_A ", 0x0140 }, 2171 { "TVO_DATA_DELAY_B ", 0x0144 }, 2172 { "TVO_SYNC_PAT_ACCUM ", 0x0108 }, 2173 { "TVO_SYNC_PAT_EXPECT ", 0x0110 }, 2174 { "TVO_SYNC_THRESHOLD ", 0x010c }, 2175 { "TV_DAC_CNTL ", 0x0280 }, 2176 { "TV_DTO_INCREMENTS ", 0x0390 }, 2177 { "TV_PLL_CNTL ", 0x00c0 }, 2178 { "TV_PLL_FINE_CNTL ", 0x00b8 }, 2179 { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 }, 2180 { "UPSAMP_COEFF0_0 ", 0x0340 }, 2181 { "UPSAMP_COEFF0_1 ", 0x0344 }, 2182 { "UPSAMP_COEFF0_2 ", 0x0348 }, 2183 { "UPSAMP_COEFF1_0 ", 0x034c }, 2184 { "UPSAMP_COEFF1_1 ", 0x0350 }, 2185 { "UPSAMP_COEFF1_2 ", 0x0354 }, 2186 { "UPSAMP_COEFF2_0 ", 0x0358 }, 2187 { "UPSAMP_COEFF2_1 ", 0x035c }, 2188 { "UPSAMP_COEFF2_2 ", 0x0360 }, 2189 { "UPSAMP_COEFF3_0 ", 0x0364 }, 2190 { "UPSAMP_COEFF3_1 ", 0x0368 }, 2191 { "UPSAMP_COEFF3_2 ", 0x036c }, 2192 { "UPSAMP_COEFF4_0 ", 0x0370 }, 2193 { "UPSAMP_COEFF4_1 ", 0x0374 }, 2194 { "UPSAMP_COEFF4_2 ", 0x0378 }, 2195 { "UV_ADR ", 0x0300 }, 2196 { "VBI_20BIT_CNTL ", 0x02d0 }, 2197 { "VBI_CC_CNTL ", 0x02c8 }, 2198 { "VBI_CONTROL ", 0x05d0 }, 2199 { "VBI_DTO_CNTL ", 0x02d4 }, 2200 { "VBI_EDS_CNTL ", 0x02cc }, 2201 { "VBI_LEVEL_CNTL ", 0x02d8 }, 2202 { "VBI_SCALER_CONTROL ", 0x060c }, 2203 { "VCOUNT ", 0x009c }, 2204 { "VDISP ", 0x0098 }, 2205 { "VFTOTAL ", 0x00a0 }, 2206 { "VIDEO_PORT_SIG ", 0x02c4 }, 2207 { "VIN_PLL_CNTL ", 0x00d4 }, 2208 { "VIN_PLL_FINE_CNTL ", 0x00d8 }, 2209 { "VIP_COMMAND_STATUS ", 0x0008 }, 2210 { "VIP_REVISION_ID ", 0x000c }, 2211 { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 }, 2212 { "VIP_VENDOR_DEVICE_ID ", 0x0000 }, 2213 { "VSCALER_CNTL1 ", 0x01c0 }, 2214 { "VSCALER_CNTL2 ", 0x01c8 }, 2215 { "VSYNC_DIFF_CNTL ", 0x03a0 }, 2216 { "VSYNC_DIFF_LIMITS ", 0x03a4 }, 2217 { "VSYNC_DIFF_RD_DATA ", 0x03a8 }, 2218 { "VS_BLANKING_CNTL ", 0x0544 }, 2219 { "VS_COUNTER_CNTL ", 0x054c }, 2220 { "VS_DETECTOR_CNTL ", 0x0540 }, 2221 { "VS_FIELD_ID_CNTL ", 0x0548 }, 2222 { "VS_FRAME_TOTAL ", 0x0550 }, 2223 { "VS_LINE_COUNT ", 0x0554 }, 2224 { "VTOTAL ", 0x0094 }, 2225 { "V_ACTIVE_WINDOW ", 0x05c4 }, 2226 { "V_DEINTERLACE_CONTROL ", 0x0608 }, 2227 { "V_SCALER_CONTROL ", 0x0604 }, 2228 { "V_VBI_WINDOW ", 0x05cc }, 2229 { "Y_FALL_CNTL ", 0x01cc }, 2230 { "Y_RISE_CNTL ", 0x01d0 }, 2231 { "Y_SAW_TOOTH_CNTL ", 0x01d4 }, 2232 {NULL, 0} 2233 }; 2234 2235 for(i=0; rt_reg_list[i].name!=NULL;i++){ 2236 RT_regr(rt_reg_list[i].addr, &data); 2237 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 2238 "register (0x%04lx) %s is equal to 0x%08x\n", 2239 rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); 2240 } 2241 2242} 2243 2244_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) 2245{ 2246 RT_regw(VIP_CLKOUT_CNTL, 0x0); 2247 RT_regw(VIP_HCOUNT, 0x0); 2248 RT_regw(VIP_VCOUNT, 0x0); 2249 RT_regw(VIP_DFCOUNT, 0x0); 2250 #if 0 2251 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2252 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2253 #endif 2254 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0); 2255} 2256 2257 2258_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) 2259{ 2260/* RT_regw(VIP_HW_DEBUG, 0x200); */ 2261/* RT_regw(VIP_INT_CNTL, 0x0); 2262 RT_regw(VIP_GPIO_INOUT, 0x10090000); 2263 RT_regw(VIP_GPIO_INOUT, 0x340b0000); */ 2264/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */ 2265 RT_regw(VIP_CLKOUT_CNTL, 0x29); 2266#if 1 2267 RT_regw(VIP_HCOUNT, 0x1d1); 2268 RT_regw(VIP_VCOUNT, 0x1e3); 2269#else 2270 RT_regw(VIP_HCOUNT, 0x322); 2271 RT_regw(VIP_VCOUNT, 0x151); 2272#endif 2273 RT_regw(VIP_DFCOUNT, 0x01); 2274/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */ 2275 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2276 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2277/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */ 2278 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f); 2279/* RT_regw(VIP_ADC_CNTL, 0x02a420a8); 2280 RT_regw(VIP_COMB_CNTL_0, 0x0d438083); 2281 RT_regw(VIP_COMB_CNTL_2, 0x06080102); 2282 RT_regw(VIP_HS_MINMAXWIDTH, 0x462f); 2283 ... 2284 */ 2285/* 2286 RT_regw(VIP_HS_PULSE_WIDTH, 0x359); 2287 RT_regw(VIP_HS_PLL_ERROR, 0xab6); 2288 RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8); 2289 RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005); 2290 */ 2291} 2292 2293