Lines Matching refs:Clock
164 static void chipsClockSave(ScrnInfoPtr pScrn, CHIPSClockPtr Clock);
165 static void chipsClockLoad(ScrnInfoPtr pScrn, CHIPSClockPtr Clock);
167 int no, CHIPSClockPtr Clock);
168 static void chipsCalcClock(ScrnInfoPtr pScrn, int Clock,
345 15000, /* Clock frequency */
389 15000, /* Clock frequency */
431 11970, /* Clock frequency */
1166 * Setup the ClockRanges, which describe what clock ranges are available,
1337 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
2037 /* We use a programmable clock */
2042 SaveClk->Clock = 0;
2046 /* Set the maximum memory clock. */
2096 "Dot clock %i: %7.3f MHz",i,
2118 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Force CRT Clock index to %d\n",
2124 "Force FP Clock index to %d\n", indx);
2133 "FP Clock index forced to %d\n", cPtr->FPclkInx);
2139 "Force FP Clock index to %d\n", indx);
2147 "CRT Clock index forced to %d\n", cPtr->CRTclkInx);
2152 /* Probe the memory clock currently in use */
2171 "Using memory clock of %7.3f MHz\n",
2174 /* Only alter the memory clock if the desired memory clock differs
2192 "Memory clock of %7.3f MHz exceeds limit of %7.3f MHz\n",
2197 "Probed memory clock of %7.3f MHz\n",
2202 /* Set the min/max pixel clock */
2235 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
2239 /* RAS/CAS. Extra byte per memory clock needed if framebuffer used */
2284 "User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
2289 "Max pixel clock is %7.3f MHz\n",
2294 * if FPclock <= MaxClock : don't modify the FP clock.
2302 "FP clock %7.3f MHz requested\n",real);
2307 "FP clock %7.3f MHz requested\n",real);
2312 "FP clock %7.3f MHz requested\n",real);
2317 "FP clock %7.3f MHz requested\n",real);
2330 "FP clock set to %7.3f MHz\n",
2365 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
2718 /* Clock type */
2727 "Using external clock generator\n");
2732 "Using internal clock generator\n");
2746 SaveClk->Clock = CRT_TEXT_CLK_FREQ;
2749 SaveClk->Clock = chipsGetHWClock(pScrn);
2750 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using textclock clock %i.\n",
2751 SaveClk->Clock);
2768 pScrn->clock[i] = cPtr->pEnt->device->clock[i];
2774 /* Set the min pixel clock */
2777 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
2779 /* maximal clock */
2808 "User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
2813 "Max pixel clock is %7.3f MHz\n",
2833 CHIPSClockPtr SaveClk = &(cPtr->SavedReg.Clock);
3413 /* We use a programmable clock */
3434 SaveClk->Clock = ((cPtr->PanelType & ChipsLCDProbed) ?
3438 SaveClk->Clock = chipsGetHWClock(pScrn);
3439 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using textclock clock %i.\n",
3440 SaveClk->Clock);
3457 pScrn->clock[i] = cPtr->pEnt->device->clock[i];
3462 /* Set the min pixel clock */
3465 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Min pixel clock is %7.3f MHz\n",
3467 /* Set the max pixel clock */
3504 "User max pixel clock of %7.3f MHz overrides %7.3f MHz limit\n",
3509 "Max pixel clock is %7.3f MHz\n",
3513 /* FP clock */
3535 "FP clock %7.3f MHz requested\n",real);
3550 "FP clock set to %7.3f MHz\n",
3555 "FP clock option not supported for this chipset\n");
3558 /* Memory Clock */
3583 "Using memory clock of %7.3f MHz\n",
3588 "Memory clock of %7.3f MHz exceeds limit of "
3598 "Memory clock option not supported for this chipset\n");
4664 chipsClockSave(ScrnInfoPtr pScrn, CHIPSClockPtr Clock)
4672 Clock->msr = hwp->readMiscOut(hwp)&0xFE; /* save standard VGA clock reg */
4675 /* save alternate clock select reg.*/
4676 /* The 69030 FP clock select is at FR01 instead */
4684 Clock->fr03 = cPtr->readFR(cPtr, 0x01);
4686 Clock->fr03 = cPtr->readFR(cPtr, 0x03);
4687 if (!Clock->Clock) { /* save HiQV console clock */
4701 Clock->fcr = hwp->readFCR(hwp);
4702 Clock->xr02 = cPtr->readXR(cPtr, 0x02);
4703 Clock->xr54 = cPtr->readXR(cPtr, 0x54); /* save alternate clock select reg.*/
4709 Clock->xr54 = cPtr->readXR(cPtr, 0x54); /* save alternate clock select reg.*/
4710 Clock->xr33 = cPtr->readXR(cPtr, 0x33); /* get status of MCLK/VCLK sel reg.*/
4720 int no, CHIPSClockPtr Clock )
4738 Clock->msr = cPtr->CRTclkInx << 2;
4739 Clock->fr03 = cPtr->FPclkInx << 2;
4740 Clock->Clock = mode ? mode->Clock : 0;
4742 Clock->FPClock = mode ? mode->Clock : 0;
4744 Clock->FPClock = cPtr->FPclock;
4748 Clock->msr = (no == 4 ? 3 << 2: (no & 0x01) << 2);
4749 Clock->xr54 = Clock->msr;
4750 Clock->xr33 = no > 1 ? 0x80 : 0;
4752 Clock->msr = 3 << 2;
4753 Clock->xr33 = 0;
4754 Clock->xr54 = Clock->msr;
4763 * have one programmable clock which needs to
4779 Clock->Clock = cPtr->FPclock;
4781 Clock->Clock = mode ? mode->SynthClock : 0;
4786 Clock->msr = 3 << 2;
4787 Clock->fcr = no & 0x03;
4788 Clock->xr02 = 0;
4789 Clock->xr54 = Clock->msr & (Clock->fcr << 4);
4791 Clock->msr = (no << 2) & 0x4;
4792 Clock->fcr = 0;
4793 Clock->xr02 = no & 0x02;
4794 Clock->xr54 = Clock->msr;
4798 Clock->msr = no << 2;
4801 Clock->msr = (no == 2 ? 3 << 2: (no & 0x01) << 2);
4802 Clock->xr33 = 0;
4804 Clock->msr = 3 << 2;
4805 Clock->xr33 = 0;
4806 Clock->Clock = mode ? mode->SynthClock : 0;
4810 Clock->msr |= (hwp->readMiscOut(hwp) & 0xF2);
4868 chipsClockLoad(ScrnInfoPtr pScrn, CHIPSClockPtr Clock)
4881 /* save alternate clock select reg. */
4882 /* The 69030 FP clock select is at FR01 instead */
4887 /* select fixed clock 0 before tampering with VCLK select */
4890 /* The 69030 FP clock select is at FR01 instead */
4895 if (!Clock->Clock) { /* Hack to load saved console clock */
4915 chipsCalcClock(pScrn, Clock->Clock, vclk);
4921 if (Clock->FPClock) {
4923 chipsCalcClock(pScrn, Clock->FPClock, vclk);
4933 /* The 69030 FP clock select is at FR01 instead */
4936 (Clock->fr03 & 0x0C)));
4939 (Clock->fr03 & 0x0C)));
4944 /* Only write to soft clock registers if we really need to */
4946 /* select fixed clock 0 before tampering with VCLK select */
4949 chipsCalcClock(pScrn, Clock->Clock, vclk);
4963 cPtr->writeXR(cPtr, 0x02, ((tmp02 & ~0x02) | (Clock->xr02 & 0x02)));
4964 cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF0) | (Clock->xr54 & ~0xF0)));
4965 hwp->writeFCR(hwp, (tmpfcr & ~0x03) & Clock->fcr);
4970 /* Only write to soft clock registers if we really need to */
4972 /* select fixed clock 0 before tampering with VCLK select */
4976 /* if user wants to set the memory clock, do it first */
4986 chipsCalcClock(pScrn, Clock->Clock, vclk);
4994 cPtr->writeXR(cPtr, 0x33, ((tmp33 & ~0x80) | (Clock->xr33 & 0x80)));
4995 cPtr->writeXR(cPtr, 0x54, ((tmp54 & 0xF3) | (Clock->xr54 & ~0xF3)));
4998 hwp->writeMiscOut(hwp, (Clock->msr & 0xFE) |
5006 * This is Ken Raeburn's <raeburn@raeburn.org> clock
5011 chipsCalcClock(ScrnInfoPtr pScrn, int Clock, unsigned char *vclk)
5028 /* Hack to deal with problem of Toshiba 720CDT clock */
5035 * not documented in the Clock Synthesizer doc in rev 1.0 of the
5041 * + XR30[5] = 1, reference clock is divided by 5
5048 * + XRCB[1] = 1, reference clock is divided by 5
5062 * + The 690x0 has no reference clock divider, so PSN must
5068 target = Clock * 1000;
5148 (float)(Clock / 1000.), vclk[0], vclk[1], vclk[2]);
5183 /* save clock */
5184 chipsClockSave(pScrn, &ChipsSave->Clock);
5325 /* init clock */
5326 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
5335 if (((ChipsNew->Clock.FPClock + ChipsNew->Clock.Clock) *
5668 if (cPtr->PanelType & ChipsDD) /* Shift Clock Mask. Use to get */
5859 /* init clock */
5860 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
5985 /* bit6-4: Clock Divide (CD) */
5986 /* 000, Shift Clock Freq = Dot Clock Freq; */
6101 /* init clock */
6102 if (!chipsClockFind(pScrn, mode, mode->ClockIndex, &ChipsNew->Clock)) {
6281 * line total, 0x2D specifies the number of clock ticks? to
6436 /* bit6-4: Clock Divide (CD) */
6437 /* 000, Shift Clock Freq = Dot Clock Freq; */
6554 /* set the clock */
6555 chipsClockLoad(pScrn, &ChipsReg->Clock);
6663 /* set mem clock */
6680 /* Don't touch alternate clock select reg. */
6682 /* restore the non clock bits */
6694 /* restore the non clock bits */
6740 tmp = cPtr->readXR(cPtr, 0x54); /* restore the non clock bits */
Indexes created Fri Jul 03 00:25:33 UTC 2026