1 /* $NetBSD: asc_tcds.c,v 1.27 2026/01/02 23:33:59 nia Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the author may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: asc_tcds.c,v 1.27 2026/01/02 23:33:59 nia Exp $"); 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/buf.h> 66 67 #include <dev/scsipi/scsi_all.h> 68 #include <dev/scsipi/scsipi_all.h> 69 #include <dev/scsipi/scsiconf.h> 70 71 #include <dev/ic/ncr53c9xreg.h> 72 #include <dev/ic/ncr53c9xvar.h> 73 74 #include <sys/bus.h> 75 76 #include <dev/tc/tcvar.h> 77 #include <dev/tc/tcdsreg.h> 78 #include <dev/tc/tcdsvar.h> 79 80 struct asc_softc { 81 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 82 bus_space_tag_t sc_bst; /* bus space tag */ 83 bus_space_handle_t sc_scsi_bsh; /* ASC register handle */ 84 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 85 bus_dmamap_t sc_dmamap; /* bus dmamap */ 86 uint8_t **sc_dmaaddr; 87 size_t *sc_dmalen; 88 size_t sc_dmasize; 89 unsigned sc_flags; 90 #define ASC_ISPULLUP 0x01 91 #define ASC_DMAACTIVE 0x02 92 #define ASC_MAPLOADED 0x04 93 struct tcds_slotconfig *sc_tcds; /* DMA/slot info lives here */ 94 }; 95 96 static int asc_tcds_match(device_t, cfdata_t, void *); 97 static void asc_tcds_attach(device_t, device_t, void *); 98 99 CFATTACH_DECL_NEW(asc_tcds, sizeof(struct asc_softc), 100 asc_tcds_match, asc_tcds_attach, NULL, NULL); 101 102 /* 103 * Functions and the switch for the MI code. 104 */ 105 static uint8_t asc_read_reg(struct ncr53c9x_softc *, int); 106 static void asc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 107 static int tcds_dma_isintr(struct ncr53c9x_softc *); 108 static void tcds_dma_reset(struct ncr53c9x_softc *); 109 static int tcds_dma_intr(struct ncr53c9x_softc *); 110 static int tcds_dma_setup(struct ncr53c9x_softc *, uint8_t **, 111 size_t *, int, size_t *); 112 static void tcds_dma_go(struct ncr53c9x_softc *); 113 static void tcds_dma_stop(struct ncr53c9x_softc *); 114 static int tcds_dma_isactive(struct ncr53c9x_softc *); 115 static void tcds_clear_latched_intr(struct ncr53c9x_softc *); 116 117 static struct ncr53c9x_glue asc_tcds_glue = { 118 asc_read_reg, 119 asc_write_reg, 120 tcds_dma_isintr, 121 tcds_dma_reset, 122 tcds_dma_intr, 123 tcds_dma_setup, 124 tcds_dma_go, 125 tcds_dma_stop, 126 tcds_dma_isactive, 127 tcds_clear_latched_intr, 128 }; 129 130 static int 131 asc_tcds_match(device_t parent, cfdata_t cf, void *aux) 132 { 133 134 /* We always exist. */ 135 return 1; 136 } 137 138 #define DMAMAX(a) (PAGE_SIZE - ((a) & (PAGE_SIZE - 1))) 139 140 /* 141 * Attach this instance, and then all the sub-devices 142 */ 143 static void 144 asc_tcds_attach(device_t parent, device_t self, void *aux) 145 { 146 struct asc_softc *asc = device_private(self); 147 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 148 struct tcdsdev_attach_args *tcdsdev = aux; 149 int error; 150 151 /* 152 * Set up glue for MI code early; we use some of it here. 153 */ 154 sc->sc_dev = self; 155 sc->sc_glue = &asc_tcds_glue; 156 157 asc->sc_bst = tcdsdev->tcdsda_bst; 158 asc->sc_scsi_bsh = tcdsdev->tcdsda_bsh; 159 asc->sc_tcds = tcdsdev->tcdsda_sc; 160 161 /* 162 * The TCDS ASIC cannot DMA across 8k boundaries, and this 163 * driver is written such that each DMA segment gets a new 164 * call to tcds_dma_setup(). Thus, the DMA map only needs 165 * to support 8k transfers. 166 */ 167 asc->sc_dmat = tcdsdev->tcdsda_dmat; 168 if ((error = bus_dmamap_create(asc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 169 PAGE_SIZE, BUS_DMA_NOWAIT, &asc->sc_dmamap)) < 0) { 170 aprint_error(": failed to create DMA map, error = %d\n", error); 171 return; 172 } 173 174 sc->sc_id = tcdsdev->tcdsda_id; 175 sc->sc_freq = tcdsdev->tcdsda_freq; 176 177 /* gimme MHz */ 178 sc->sc_freq /= 1000000; 179 180 tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); 181 182 /* 183 * XXX More of this should be in ncr53c9x_attach(), but 184 * XXX should we really poke around the chip that much in 185 * XXX the MI code? Think about this more... 186 */ 187 188 /* 189 * Set up static configuration info. 190 */ 191 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 192 sc->sc_cfg2 = NCRCFG2_SCSI2; 193 sc->sc_cfg3 = NCRCFG3_CDB; 194 if (sc->sc_freq > 25) 195 sc->sc_cfg3 |= NCRF9XCFG3_FCLK; 196 sc->sc_rev = tcdsdev->tcdsda_variant; 197 if (tcdsdev->tcdsda_fast) { 198 sc->sc_features |= NCR_F_FASTSCSI; 199 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 200 } 201 202 /* 203 * XXX minsync and maxxfer _should_ be set up in MI code, 204 * XXX but it appears to have some dependency on what sort 205 * XXX of DMA we're hooked up to, etc. 206 */ 207 208 /* 209 * This is the value used to start sync negotiations 210 * Note that the NCR register "SYNCTP" is programmed 211 * in "clocks per byte", and has a minimum value of 4. 212 * The SCSI period used in negotiation is one-fourth 213 * of the time (in nanoseconds) needed to transfer one byte. 214 * Since the chip's clock is given in MHz, we have the following 215 * formula: 4 * period = (1000 / freq) * 4 216 */ 217 sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; 218 219 sc->sc_maxxfer = 64 * 1024; 220 221 /* Do the common parts of attachment. */ 222 sc->sc_adapter.adapt_minphys = minphys; 223 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 224 ncr53c9x_attach(sc); 225 } 226 227 static void 228 tcds_dma_reset(struct ncr53c9x_softc *sc) 229 { 230 struct asc_softc *asc = (struct asc_softc *)sc; 231 232 /* TCDS SCSI disable/reset/enable. */ 233 tcds_scsi_reset(asc->sc_tcds); /* XXX */ 234 235 if (asc->sc_flags & ASC_MAPLOADED) 236 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 237 asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); 238 } 239 240 /* 241 * start a DMA transfer or keep it going 242 */ 243 int 244 tcds_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 245 int ispullup, size_t *dmasize) 246 { 247 struct asc_softc *asc = (struct asc_softc *)sc; 248 struct tcds_slotconfig *tcds = asc->sc_tcds; 249 size_t size; 250 uint32_t dic; 251 252 NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, 253 (int)*asc->sc_dmalen, *asc->sc_dmaaddr, 254 (ispullup) ? "IN" : "OUT")); 255 256 /* 257 * the rules say we cannot transfer more than the limit 258 * of this DMA chip (64k) and we cannot cross a 8k boundary. 259 */ 260 size = uimin(*dmasize, DMAMAX((size_t)*addr)); 261 asc->sc_dmaaddr = addr; 262 asc->sc_dmalen = len; 263 asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0; 264 *dmasize = asc->sc_dmasize = size; 265 266 NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); 267 268 if (size == 0) 269 return 0; 270 271 if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, size, 272 NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { 273 /* 274 * XXX Should return an error, here, but the upper-layer 275 * XXX doesn't check the return value! 276 */ 277 panic("%s: dmamap load failed", __func__); 278 } 279 280 /* synchronize dmamap contents with memory image */ 281 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 0, size, 282 (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 283 284 /* load address, set/clear unaligned transfer and read/write bits. */ 285 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, 286 asc->sc_dmamap->dm_segs[0].ds_addr >> 2); 287 dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); 288 dic &= ~TCDS_DIC_ADDRMASK; 289 dic |= asc->sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; 290 if (ispullup) 291 dic |= TCDS_DIC_WRITE; 292 else 293 dic &= ~TCDS_DIC_WRITE; 294 bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); 295 296 asc->sc_flags |= ASC_MAPLOADED; 297 return 0; 298 } 299 300 static void 301 tcds_dma_go(struct ncr53c9x_softc *sc) 302 { 303 struct asc_softc *asc = (struct asc_softc *)sc; 304 305 /* mark unit as DMA-active */ 306 asc->sc_flags |= ASC_DMAACTIVE; 307 308 /* start DMA */ 309 tcds_dma_enable(asc->sc_tcds, 1); 310 } 311 312 static void 313 tcds_dma_stop(struct ncr53c9x_softc *sc) 314 { 315 #if 0 316 struct asc_softc *asc = (struct asc_softc *)sc; 317 #endif 318 319 /* 320 * XXX STOP DMA HERE! 321 */ 322 } 323 324 /* 325 * Pseudo (chained) interrupt from the asc driver to kick the 326 * current running DMA transfer. Called from ncr53c9x_intr() 327 * for now. 328 * 329 * return 1 if it was a DMA continue. 330 */ 331 static int 332 tcds_dma_intr(struct ncr53c9x_softc *sc) 333 { 334 struct asc_softc *asc = (struct asc_softc *)sc; 335 struct tcds_slotconfig *tcds = asc->sc_tcds; 336 int trans, resid; 337 uint32_t tcl, tcm; 338 uint32_t dud, dudmask, *addr; 339 bus_addr_t pa; 340 341 NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); 342 343 if (tcds_scsi_iserr(tcds)) 344 return 0; 345 346 /* This is an "assertion" :) */ 347 if ((asc->sc_flags & ASC_DMAACTIVE) == 0) 348 panic("%s: DMA wasn't active", __func__); 349 350 /* DMA has stopped */ 351 tcds_dma_enable(tcds, 0); 352 asc->sc_flags &= ~ASC_DMAACTIVE; 353 354 if (asc->sc_dmasize == 0) { 355 /* A "Transfer Pad" operation completed */ 356 tcl = NCR_READ_REG(sc, NCR_TCL); 357 tcm = NCR_READ_REG(sc, NCR_TCM); 358 NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", 359 tcl | (tcm << 8), tcl, tcm)); 360 return 0; 361 } 362 363 resid = 0; 364 if ((asc->sc_flags & ASC_ISPULLUP) == 0 && 365 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 366 NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); 367 DELAY(1); 368 } 369 370 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); 371 resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; 372 373 trans = asc->sc_dmasize - resid; 374 if (trans < 0) { /* transferred < 0 ? */ 375 printf("tcds_dma %d: xfer (%d) > req (%d)\n", 376 tcds->sc_slot, trans, (int)asc->sc_dmasize); 377 trans = asc->sc_dmasize; 378 } 379 380 NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 381 tcl, tcm, trans, resid)); 382 383 *asc->sc_dmalen -= trans; 384 *asc->sc_dmaaddr += trans; 385 386 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 387 0, asc->sc_dmamap->dm_mapsize, 388 (sc->sc_flags & ASC_ISPULLUP) ? 389 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 390 391 /* 392 * Clean up unaligned DMAs into main memory. 393 */ 394 if (asc->sc_flags & ASC_ISPULLUP) { 395 /* Handle unaligned starting address, length. */ 396 dud = bus_space_read_4(tcds->sc_bst, 397 tcds->sc_bsh, tcds->sc_dud0); 398 if ((dud & TCDS_DUD0_VALIDBITS) != 0) { 399 addr = (uint32_t *)((paddr_t)*asc->sc_dmaaddr & ~0x3); 400 dudmask = 0; 401 if (dud & TCDS_DUD0_VALID00) 402 panic("%s: dud0 byte 0 valid", __func__); 403 if (dud & TCDS_DUD0_VALID01) 404 dudmask |= TCDS_DUD_BYTE01; 405 if (dud & TCDS_DUD0_VALID10) 406 dudmask |= TCDS_DUD_BYTE10; 407 #ifdef DIAGNOSTIC 408 if (dud & TCDS_DUD0_VALID11) 409 dudmask |= TCDS_DUD_BYTE11; 410 #endif 411 NCR_DMA(("dud0 at %p dudmask 0x%x\n", 412 addr, dudmask)); 413 *addr = (*addr & ~dudmask) | (dud & dudmask); 414 } 415 dud = bus_space_read_4(tcds->sc_bst, 416 tcds->sc_bsh, tcds->sc_dud1); 417 if ((dud & TCDS_DUD1_VALIDBITS) != 0) { 418 pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, 419 tcds->sc_sda) << 2; 420 dudmask = 0; 421 if (dud & TCDS_DUD1_VALID00) 422 dudmask |= TCDS_DUD_BYTE00; 423 if (dud & TCDS_DUD1_VALID01) 424 dudmask |= TCDS_DUD_BYTE01; 425 if (dud & TCDS_DUD1_VALID10) 426 dudmask |= TCDS_DUD_BYTE10; 427 #ifdef DIAGNOSTIC 428 if (dud & TCDS_DUD1_VALID11) 429 panic("%s: dud1 byte 3 valid", __func__); 430 #endif 431 NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", 432 pa, dudmask)); 433 /* XXX Fix TC_PHYS_TO_UNCACHED() */ 434 #if defined(__alpha__) 435 addr = (uint32_t *)ALPHA_PHYS_TO_K0SEG(pa); 436 #elif defined(__mips__) 437 addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(pa); 438 #elif defined(__vax__) 439 addr = (uint32_t *)VAX_PHYS_TO_S0(pa); 440 #else 441 #error TURBOchannel only exists on DECs, folks... 442 #endif 443 *addr = (*addr & ~dudmask) | (dud & dudmask); 444 } 445 /* XXX deal with saved residual byte? */ 446 } 447 448 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 449 asc->sc_flags &= ~ASC_MAPLOADED; 450 451 return 0; 452 } 453 454 /* 455 * Glue functions. 456 */ 457 static uint8_t 458 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 459 { 460 struct asc_softc *asc = (struct asc_softc *)sc; 461 uint32_t v; 462 463 v = bus_space_read_4(asc->sc_bst, asc->sc_scsi_bsh, 464 reg * sizeof(uint32_t)); 465 466 return v & 0xff; 467 } 468 469 static void 470 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 471 { 472 struct asc_softc *asc = (struct asc_softc *)sc; 473 474 bus_space_write_4(asc->sc_bst, asc->sc_scsi_bsh, 475 reg * sizeof(uint32_t), val); 476 } 477 478 static int 479 tcds_dma_isintr(struct ncr53c9x_softc *sc) 480 { 481 struct asc_softc *asc = (struct asc_softc *)sc; 482 int x; 483 484 x = tcds_scsi_isintr(asc->sc_tcds, 1); 485 486 /* XXX */ 487 return x; 488 } 489 490 static int 491 tcds_dma_isactive(struct ncr53c9x_softc *sc) 492 { 493 struct asc_softc *asc = (struct asc_softc *)sc; 494 495 return (asc->sc_flags & ASC_DMAACTIVE) != 0; 496 } 497 498 static void 499 tcds_clear_latched_intr(struct ncr53c9x_softc *sc) 500 { 501 struct asc_softc *asc = (struct asc_softc *)sc; 502 503 /* Clear the TCDS interrupt bit. */ 504 (void)tcds_scsi_isintr(asc->sc_tcds, 1); 505 } 506
Indexes created Sun Oct 25 00:26:45 UTC 2026