Lines Matching refs:P3d4
312 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; */
315 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
321 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRD0[i-0xd0] ) ;
323 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRDE[i-0xdE] ) ;
328 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x97, pVBInfo->CR97);
334 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ;
409 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x09 ) ;
418 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0D ) ;
420 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ;
423 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ;
431 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
434 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
437 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
443 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
450 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
454 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
470 temp1 = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */
520 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x83 , 0x00 ) ;
534 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
536 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
540 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
542 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
549 XGINew_SetDRAMDefaultRegisterXG45( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
551 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
639 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , 0x28 ) ; //0207 temp */
640 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x36 , 0x02 ) ; //0207 temp */
673 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0xBF , 0x40 ) ;
703 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA0 , 0x72 ) ;
704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0x81 ) ;
705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA2 , 0x60 ) ;
706 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA3 , 0x20 ) ;
707 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA4 , 0x50 ) ;
708 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA5 , 0x40 ) ;
709 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA8 , 0x88 ) ;
710 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA9 , 0x10 ) ;
711 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAA , 0x80 ) ;
712 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAB , 0x01 ) ;
713 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAC , 0xF1 ) ;
714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAE , 0x80 ) ;
715 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAF , 0x45 ) ;
716 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xB7 , 0x24 ) ;
735 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x78 , 0x40 ) ;
736 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x79 , 0x0C ) ;
737 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7A , 0x34 ) ;
815 XGI_SetRegAND( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
817 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
818 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
828 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
833 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) & 0x01 ;
982 USHORT P3d4 = P3c4 + 0x10 ;
997 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */
1044 USHORT P3d4 = P3c4 + 0x10 ;
1050 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
1051 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , pVBInfo->CR97 ) ; /* CR97 */
1121 USHORT P3d4 = P3c4 + 0x10 ;
1127 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */
1174 USHORT P3d4 = P3c4 + 0x10 ;
1180 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */
1254 USHORT P3d4 = Port ,
1262 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1263 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1264 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1266 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ;
1267 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ;
1279 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1280 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1281 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1284 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ;
1285 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ;
1286 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */
1287 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ;
1288 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ;
1289 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1290 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ;
1291 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ;
1292 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1293 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ;
1294 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1295 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1296 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1300 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x00 ) ;
1301 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ;
1302 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ;
1317 USHORT P3d4 = Port ,
1331 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1332 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1333 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1337 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ;
1338 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ;
1339 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */
1340 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ;
1341 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ;
1342 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ;
1343 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1344 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ;
1345 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1346 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1347 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1349 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ;
1352 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ;
1356 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ;
1358 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ;
1373 USHORT P3d4 = Port ,
1377 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ;
1378 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ;
1379 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */
1380 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ;
1381 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */
1382 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1383 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ;
1384 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ;
1385 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1386 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ;
1387 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */
1388 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1389 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1391 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ;
1392 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ;
1415 USHORT P3d4 = Port ,
1418 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1419 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1420 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1421 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1431 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp2 ) ;
1432 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6B ) ; /* Insert read command for delay */
1446 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , temp2 ) ;
1447 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6E ) ; /* Insert read command for delay */
1456 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1465 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , temp2 ) ;
1466 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6F ) ; /* Insert read command for delay */
1474 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1475 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1483 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ;
1484 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */
1492 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ;
1498 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , temp1 ) ; /* CR45 */
1499 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , temp2 ) ; /* CR99 */
1500 XGI_SetRegOR((XGIIOADDRESS) P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1501 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1505 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1508 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1511 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1514 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1517 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ;
1519 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1521 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */
1522 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */
1523 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */
1541 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1543 XGINew_DDR2x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1545 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1561 USHORT P3d4 = Port ,
1564 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1565 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , pVBInfo->XG45CR6E[ XGINew_RAMType ] ) ;
1566 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , pVBInfo->XG45CR6F[ XGINew_RAMType ] ) ;
1567 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1568 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1569 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1574 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp );
1578 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1579 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1587 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ;
1588 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */
1596 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ;
1601 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x40 , temp );
1608 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , temp );
1615 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x42 , temp );
1621 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x04 , k * 0x04 );
1626 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x03 , i * 0x01 );
1629 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x44 , j * 0x08 );
1634 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , j * 0x08 ) ; /* CR45 */
1636 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x84 ) ;
1637 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ;
1638 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , 0x22 ) ;
1639 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ;
1642 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1644 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1647 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1649 XGI_SetReg((XGIIOADDRESS) P3d4 , 0xC8 , 0x04 ) ;
1652 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1654 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x40 ) ;
1657 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ;
1659 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */
1660 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */
1661 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */
1662 XGI_SetReg((XGIIOADDRESS) P3d4, 0x8D, 0x87); /* CR8D */
1664 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
2412 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ;
2440 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ;
2973 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3462 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
3508 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 ) ;
3531 tempcx = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ;
3532 tempcx |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3536 CR3CData = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3c ) ;
3554 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3555 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3567 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ;
3568 temp |= XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ;
3569 temp |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3635 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x30 , tempcl ) ;
3637 CR31Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) ;
3644 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x31 , CR31Data ) ;
3646 CR38Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ;
3649 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x38 , CR38Data ) ;
3669 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3670 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3674 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3675 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0xC0;
3679 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3680 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3681 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3683 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3685 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3687 XGI_SetRegAND( (XGIIOADDRESS)pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3704 bCR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ;
3705 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3706 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x07;
3707 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , bCR4A ) ;
3712 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3713 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x30 , 0x21 ) ;
3717 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3720 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3727 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ;
3728 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3729 CR38 = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ;
3733 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ;
3738 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ;
3747 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ;
3748 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3749 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ;
3759 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ;