Lines Matching refs:USHORT
65 USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48},
75 static const USHORT XGINew_SDRDRAM_TYPE[13][5]=
92 static const USHORT XGINew_DDRDRAM_TYPE[4][5]=
100 static const USHORT XGINew_DDRDRAM_TYPE340[4][5]=
109 USHORT XGINew_DDRDRAM_TYPE20[12][5]=
129 static void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO, USHORT,
131 static void XGINew_SetDRAMDefaultRegisterXG45(PXGI_HW_DEVICE_INFO, USHORT,
136 UCHAR XGINew_ChannelAB, const USHORT DRAMTYPE_TABLE[][5],
140 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
141 static USHORT XGINew_SetDRAMSizeReg(int index,
142 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
145 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
148 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
150 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
152 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
154 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo);
156 static int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5],
158 static int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5],
175 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
177 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
179 USHORT P3c4, PVB_DEVICE_INFO pVBInfo);
181 USHORT Port, PVB_DEVICE_INFO pVBInfo);
183 USHORT Port, PVB_DEVICE_INFO pVBInfo);
185 USHORT Port, PVB_DEVICE_INFO pVBInfo);
188 const USHORT XGINew_DDRDRAM_TYPE[][5], PVB_DEVICE_INFO pVBInfo);
196 static void SetPowerConsume(PXGI_HW_DEVICE_INFO, USHORT);
197 static void XGINew_DDR1x_MRS_XG20(USHORT, PVB_DEVICE_INFO);
201 static int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr,
203 static int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr,
230 USHORT Mclockdata[ 30 ] , Eclockdata[ 30 ] ;
264 XGI_SetRegByte((XGIIOADDRESS) ( USHORT )( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
656 USHORT BaseAddr2nd = (USHORT)(ULONG)HwDeviceExtension->pj2ndIOAddress ;
658 USHORT BaseAddr2nd = (USHORT)HwDeviceExtension->pj2ndIOAddress ;
660 USHORT XGINew_P3C3 = pVBInfo->BaseAddr + VIDEO_SUBSYSTEM_ENABLE_PORT ;
661 USHORT XGINew_P3CC = pVBInfo->BaseAddr + MISC_OUTPUT_REG_READ_PORT ;
662 USHORT XGINew_2ndP3C3 = BaseAddr2nd + VIDEO_SUBSYSTEM_ENABLE_PORT ;
663 USHORT XGINew_2ndP3D4 = BaseAddr2nd + CRTC_ADDRESS_PORT_COLOR ;
664 USHORT XGINew_2ndP3C4 = BaseAddr2nd + SEQ_ADDRESS_PORT ;
665 USHORT XGINew_2ndP3C2 = BaseAddr2nd + MISC_OUTPUT_REG_WRITE_PORT ;
670 pVBInfo->BaseAddr = (USHORT)HwDeviceExtension->pjIOAddress ;
864 USHORT data ;
882 void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
932 void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
979 void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4,
982 USHORT P3d4 = P3c4 + 0x10 ;
1042 void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1044 USHORT P3d4 = P3c4 + 0x10 ;
1119 void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1121 USHORT P3d4 = P3c4 + 0x10 ;
1172 void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
1174 USHORT P3d4 = P3c4 + 0x10 ;
1252 USHORT Port, PVB_DEVICE_INFO pVBInfo)
1254 USHORT P3d4 = Port ,
1315 USHORT Port, PVB_DEVICE_INFO pVBInfo)
1317 USHORT P3d4 = Port ,
1371 USHORT Port, PVB_DEVICE_INFO pVBInfo)
1373 USHORT P3d4 = Port ,
1410 void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo)
1415 USHORT P3d4 = Port ,
1556 void XGINew_SetDRAMDefaultRegisterXG45( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo)
1561 USHORT P3d4 = Port ,
1678 USHORT data ;
1742 USHORT data ;
1749 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */
1760 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */
1772 USHORT data ;
1779 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /*disable read cache*/
1788 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /*enable read cache*/
1834 USHORT data ;
1866 const USHORT XGINew_DDRDRAM_TYPE[][5],
1869 USHORT data ;
1901 void XGINew_SetDRAMSizingType(int index , const USHORT DRAMTYPE_TABLE[][5],
1904 USHORT data ;
1919 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo)
1921 USHORT data ;
1957 const USHORT DRAMTYPE_TABLE[][5],
1960 USHORT data ;
1994 int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5],
2026 int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5],
2058 int XGINew_CheckRank(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5],
2094 const USHORT DRAMTYPE_TABLE[][5],
2098 USHORT data ;
2137 int XGINew_CheckRanks(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5],
2165 const USHORT DRAMTYPE_TABLE[][5],
2222 USHORT XGINew_SetDRAMSizeReg(int index, const USHORT DRAMTYPE_TABLE[][5],
2225 USHORT data = 0 , memsize = 0 ;
2271 USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo)
2273 USHORT data = 0 , memsize = 0 ;
2321 int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr,
2358 int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr,
2779 USHORT memsize , addr ;
2833 USHORT memsize , addr ;
2931 void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT XGI_P3d4Port )
2966 /* pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ; */
3396 void XGINew_DDR1x_MRS_XG20( USHORT P3c4 , PVB_DEVICE_INFO pVBInfo)
3458 pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ;
3506 USHORT tempbx=0 , temp , tempcx , CR3CData;
3565 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;