1 /* $NetBSD: viaide.c,v 1.108 2026/07/06 17:40:42 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.108 2026/07/06 17:40:42 andvar Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pciidereg.h> 37 #include <dev/pci/pciidevar.h> 38 #include <dev/pci/pciide_apollo_reg.h> 39 40 static int via_pcib_match(const struct pci_attach_args *); 41 static void via_chip_map(struct pciide_softc *, 42 const struct pci_attach_args *); 43 static void via_mapchan(const struct pci_attach_args *, 44 struct pciide_channel *, 45 pcireg_t, int (*)(void *)); 46 static void via_mapregs_compat_native(const struct pci_attach_args *, 47 struct pciide_channel *); 48 static int via_sata_chip_map_common(struct pciide_softc *, 49 const struct pci_attach_args *); 50 static void via_sata_chip_map(struct pciide_softc *, 51 const struct pci_attach_args *, int); 52 static void via_sata_chip_map_6(struct pciide_softc *, 53 const struct pci_attach_args *); 54 static void via_sata_chip_map_7(struct pciide_softc *, 55 const struct pci_attach_args *); 56 static void via_sata_chip_map_new(struct pciide_softc *, 57 const struct pci_attach_args *); 58 static void via_setup_channel(struct ata_channel *); 59 60 static int viaide_match(device_t, cfdata_t, void *); 61 static void viaide_attach(device_t, device_t, void *); 62 static const struct pciide_product_desc * 63 viaide_lookup(pcireg_t); 64 static bool viaide_suspend(device_t, const pmf_qual_t *); 65 static bool viaide_resume(device_t, const pmf_qual_t *); 66 67 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 68 viaide_match, viaide_attach, pciide_detach, NULL); 69 70 static const struct pciide_product_desc pciide_amd_products[] = { 71 { PCI_PRODUCT_AMD_PBC756_IDE, 72 0, 73 "AMD AMD756 IDE Controller", 74 via_chip_map 75 }, 76 { PCI_PRODUCT_AMD_PBC766_IDE, 77 0, 78 "AMD AMD766 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC768_IDE, 82 0, 83 "AMD AMD768 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC8111_IDE, 87 0, 88 "AMD AMD8111 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_CS5536_IDE, 92 0, 93 "AMD CS5536 IDE Controller", 94 via_chip_map 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static const struct pciide_product_desc pciide_nvidia_products[] = { 104 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 105 0, 106 "NVIDIA nForce IDE Controller", 107 via_chip_map 108 }, 109 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 110 0, 111 "NVIDIA nForce2 IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 115 0, 116 "NVIDIA nForce2 Ultra 400 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 120 0, 121 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 122 via_sata_chip_map_6 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 125 0, 126 "NVIDIA nForce3 IDE Controller", 127 via_chip_map 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 130 0, 131 "NVIDIA nForce3 250 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 135 0, 136 "NVIDIA nForce3 250 Serial ATA Controller", 137 via_sata_chip_map_6 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 145 0, 146 "NVIDIA nForce4 IDE Controller", 147 via_chip_map 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 150 0, 151 "NVIDIA nForce4 Serial ATA Controller", 152 via_sata_chip_map_6 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 160 0, 161 "NVIDIA nForce430 IDE Controller", 162 via_chip_map 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 165 0, 166 "NVIDIA nForce430 Serial ATA Controller", 167 via_sata_chip_map_6 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 175 0, 176 "NVIDIA MCP04 IDE Controller", 177 via_chip_map 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 180 0, 181 "NVIDIA MCP04 Serial ATA Controller", 182 via_sata_chip_map_6 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 190 0, 191 "NVIDIA MCP55 IDE Controller", 192 via_chip_map 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 195 0, 196 "NVIDIA MCP55 Serial ATA Controller", 197 via_sata_chip_map_6 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 205 0, 206 "NVIDIA MCP61 IDE Controller", 207 via_chip_map 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 210 0, 211 "NVIDIA MCP65 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 215 0, 216 "NVIDIA MCP73 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 220 0, 221 "NVIDIA MCP77 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 225 0, 226 "NVIDIA MCP61 Serial ATA Controller", 227 via_sata_chip_map_6 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 240 0, 241 "NVIDIA MCP65 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 260 0, 261 "NVIDIA MCP67 IDE Controller", 262 via_chip_map, 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 265 0, 266 "NVIDIA MCP67 Serial ATA Controller", 267 via_sata_chip_map_6, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { 0, 285 0, 286 NULL, 287 NULL 288 } 289 }; 290 291 static const struct pciide_product_desc pciide_via_products[] = { 292 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 293 0, 294 NULL, 295 via_chip_map, 296 }, 297 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_CX700_IDE, 303 0, 304 "VIA Technologies CX700(M2)/VX700/VX800 SATA/IDE RAID Controller", 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VX900_IDE, 313 0, 314 "VIA Technologies VX900/VX11 SATA controller", 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VX900_RAID, 318 0, 319 "VIA Technologies VX900/VX11 SATA controller (RAID mode)", 320 via_chip_map, 321 }, 322 { PCI_PRODUCT_VIATECH_VT6410_RAID, 323 0, 324 "VIA Technologies VT6410 IDE controller", 325 via_chip_map, 326 }, 327 { PCI_PRODUCT_VIATECH_VT6415_IDE, 328 0, 329 "VIA Technologies VT6415/VT6330 IDE controller", 330 via_chip_map, 331 }, 332 { PCI_PRODUCT_VIATECH_VT6420_IDE, 333 0, 334 "VIA Technologies VT6420 IDE controller", 335 via_chip_map, 336 }, 337 { PCI_PRODUCT_VIATECH_VT6421_RAID, 338 0, 339 "VIA Technologies VT6421 Serial ATA RAID Controller", 340 via_sata_chip_map_new, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237_SATA, 343 0, 344 "VIA Technologies VT8237 SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 348 0, 349 "VIA Technologies VT8237A SATA Controller", 350 via_sata_chip_map_7, 351 }, 352 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 353 0, 354 "VIA Technologies VT8237A (5337) SATA Controller", 355 via_sata_chip_map_7, 356 }, 357 /* 358 * The 0x3349 PCI ID may be reused in all modes (IDE, RAID, AHCI). 359 * ahcisata(4) will attach if AHCI mode is selected in the BIOS. 360 * Newer CE revision southbridges use it only in RAID mode. 361 */ 362 { PCI_PRODUCT_VIATECH_VT8251_SATA, 363 0, 364 "VIA Technologies VT8251 SATA Controller", 365 via_chip_map, 366 }, 367 /* 368 * The 0x5287 PCI ID is used only in IDE mode for newer 369 * VT8251 southbridge (CE) revisions. 370 */ 371 { PCI_PRODUCT_VIATECH_VT8251_SATA_2, 372 0, 373 "VIA Technologies VT8251 (5287) SATA Controller", 374 via_chip_map, 375 }, 376 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 377 0, 378 "VIA Technologies VT8237S SATA Controller", 379 via_sata_chip_map_7, 380 }, 381 { PCI_PRODUCT_VIATECH_VT8237S_SATA_RAID, 382 0, 383 "VIA Technologies VT8237S SATA Controller (RAID mode)", 384 via_sata_chip_map_7, 385 }, 386 { PCI_PRODUCT_VIATECH_VT8261_SATA, 387 0, 388 "VIA Technologies VT8261 SATA Controller", 389 via_chip_map, 390 }, 391 { PCI_PRODUCT_VIATECH_VT8261_RAID, 392 0, 393 "VIA Technologies VT8261 SATA Controller (RAID mode)", 394 via_chip_map, 395 }, 396 { 0, 397 0, 398 NULL, 399 NULL 400 } 401 }; 402 403 static const struct pciide_product_desc * 404 viaide_lookup(pcireg_t id) 405 { 406 407 switch (PCI_VENDOR(id)) { 408 case PCI_VENDOR_VIATECH: 409 return (pciide_lookup_product(id, pciide_via_products)); 410 411 case PCI_VENDOR_AMD: 412 return (pciide_lookup_product(id, pciide_amd_products)); 413 414 case PCI_VENDOR_NVIDIA: 415 return (pciide_lookup_product(id, pciide_nvidia_products)); 416 } 417 return (NULL); 418 } 419 420 static int 421 viaide_match(device_t parent, cfdata_t match, void *aux) 422 { 423 const struct pci_attach_args *pa = aux; 424 425 if (viaide_lookup(pa->pa_id) != NULL) 426 return (2); 427 return (0); 428 } 429 430 static void 431 viaide_attach(device_t parent, device_t self, void *aux) 432 { 433 const struct pci_attach_args *pa = aux; 434 struct pciide_softc *sc = device_private(self); 435 const struct pciide_product_desc *pp; 436 437 sc->sc_wdcdev.sc_atac.atac_dev = self; 438 439 pp = viaide_lookup(pa->pa_id); 440 if (pp == NULL) 441 panic("viaide_attach"); 442 pciide_common_attach(sc, pa, pp); 443 444 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 445 aprint_error_dev(self, "couldn't establish power handler\n"); 446 } 447 448 static int 449 via_pcib_match(const struct pci_attach_args *pa) 450 { 451 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 452 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 453 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 454 return (1); 455 return 0; 456 } 457 458 static bool 459 viaide_suspend(device_t dv, const pmf_qual_t *qual) 460 { 461 struct pciide_softc *sc = device_private(dv); 462 463 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 464 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 465 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 466 /* This two are VIA-only, but should be ignored by other devices. */ 467 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 468 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 469 470 return true; 471 } 472 473 static bool 474 viaide_resume(device_t dv, const pmf_qual_t *qual) 475 { 476 struct pciide_softc *sc = device_private(dv); 477 478 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 479 sc->sc_pm_reg[0]); 480 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 481 sc->sc_pm_reg[1]); 482 /* This two are VIA-only, but should be ignored by other devices. */ 483 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 484 sc->sc_pm_reg[2]); 485 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 486 sc->sc_pm_reg[3]); 487 488 return true; 489 } 490 491 static void 492 via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 493 { 494 struct pciide_channel *cp; 495 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 496 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 497 int channel; 498 u_int32_t ideconf; 499 int no_ideconf = 0; 500 int single_channel = 0; 501 pcireg_t pcib_id, pcib_class; 502 struct pci_attach_args pcib_pa; 503 504 if (pciide_chipen(sc, pa) == 0) 505 return; 506 507 switch (vendor) { 508 case PCI_VENDOR_VIATECH: 509 switch (PCI_PRODUCT(pa->pa_id)) { 510 case PCI_PRODUCT_VIATECH_VT6415_IDE: 511 /* VT6415 is a single channel IDE controller. */ 512 single_channel = 1; 513 /* FALLTHROUGH */ 514 case PCI_PRODUCT_VIATECH_VT6410_RAID: 515 /* 516 * VT6415 uses an unknown offset of the enable chip 517 * register, enable bits needs to be simulated. 518 * 519 * Some add-in VT6410 controllers have both channels 520 * disabled by default. These require explicit enabling 521 * during initialization. 522 */ 523 no_ideconf = 1; 524 /* FALLTHROUGH */ 525 case PCI_PRODUCT_VIATECH_VT6420_IDE: 526 /* FALLTHROUGH */ 527 case PCI_PRODUCT_VIATECH_CX700_IDE: 528 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 529 break; 530 case PCI_PRODUCT_VIATECH_VT8251_SATA: 531 /* FALLTHROUGH */ 532 case PCI_PRODUCT_VIATECH_VT8251_SATA_2: 533 /* FALLTHROUGH */ 534 case PCI_PRODUCT_VIATECH_VT8261_SATA: 535 /* FALLTHROUGH */ 536 case PCI_PRODUCT_VIATECH_VT8261_RAID: 537 /* FALLTHROUGH */ 538 case PCI_PRODUCT_VIATECH_VX900_IDE: 539 /* FALLTHROUGH */ 540 case PCI_PRODUCT_VIATECH_VX900_RAID: 541 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 542 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 543 break; 544 default: 545 /* 546 * VIA integrated IDE controllers share the same PCI ID 547 * between different southbridges and chipsets. 548 * To determine their DMA capabilities, get a PCI tag 549 * for the ISA bridge. 550 */ 551 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 552 goto unknown; 553 pcib_id = pcib_pa.pa_id; 554 pcib_class = pcib_pa.pa_class; 555 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 556 "VIA Technologies "); 557 switch (PCI_PRODUCT(pcib_id)) { 558 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 559 aprint_normal("VT82C586 (Apollo VP) "); 560 if(PCI_REVISION(pcib_class) >= 0x02) { 561 aprint_normal("ATA33 controller\n"); 562 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 563 } else { 564 aprint_normal("controller\n"); 565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 566 } 567 break; 568 case PCI_PRODUCT_VIATECH_VT82C596A: 569 aprint_normal("VT82C596A (Apollo Pro) "); 570 if (PCI_REVISION(pcib_class) >= 0x12) { 571 aprint_normal("ATA66 controller\n"); 572 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 573 } else { 574 aprint_normal("ATA33 controller\n"); 575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 576 } 577 break; 578 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 579 aprint_normal("VT82C686A (Apollo KX133) "); 580 if (PCI_REVISION(pcib_class) >= 0x40) { 581 aprint_normal("ATA100 controller\n"); 582 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 583 } else { 584 aprint_normal("ATA66 controller\n"); 585 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 586 } 587 break; 588 case PCI_PRODUCT_VIATECH_VT8231: 589 aprint_normal("VT8231 ATA100 controller\n"); 590 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 591 break; 592 case PCI_PRODUCT_VIATECH_VT8233: 593 aprint_normal("VT8233 ATA100 controller\n"); 594 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 595 break; 596 case PCI_PRODUCT_VIATECH_VT8233A: 597 aprint_normal("VT8233A ATA133 controller\n"); 598 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 599 break; 600 case PCI_PRODUCT_VIATECH_VT8233C: 601 aprint_normal("VT8233C ATA100 controller\n"); 602 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 603 break; 604 case PCI_PRODUCT_VIATECH_VT8235: 605 aprint_normal("VT8235 ATA133 controller\n"); 606 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 607 break; 608 case PCI_PRODUCT_VIATECH_VT8237: 609 aprint_normal("VT8237 ATA133 controller\n"); 610 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 611 break; 612 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 613 aprint_normal("VT8237A ATA133 controller\n"); 614 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 615 break; 616 case PCI_PRODUCT_VIATECH_VT8237S_ISA: 617 aprint_normal("VT8237S ATA133 controller\n"); 618 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 619 break; 620 case PCI_PRODUCT_VIATECH_CX700: 621 aprint_normal("CX700 ATA133 controller\n"); 622 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 623 break; 624 case PCI_PRODUCT_VIATECH_VT8251: 625 aprint_normal("VT8251 ATA133 controller\n"); 626 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 627 break; 628 case PCI_PRODUCT_VIATECH_VT8261: 629 aprint_normal("VT8261 ATA133 controller\n"); 630 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 631 break; 632 case PCI_PRODUCT_VIATECH_VX800: 633 aprint_normal("VX800 ATA133 controller\n"); 634 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 635 break; 636 case PCI_PRODUCT_VIATECH_VX855: 637 aprint_normal("VX855 ATA133 controller\n"); 638 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 639 break; 640 default: 641 unknown: 642 aprint_normal("unknown VIA ATA controller\n"); 643 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 644 } 645 break; 646 } 647 sc->sc_apo_regbase = APO_VIA_REGBASE; 648 break; 649 case PCI_VENDOR_AMD: 650 switch (sc->sc_pp->ide_product) { 651 case PCI_PRODUCT_AMD_PBC8111_IDE: 652 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 653 break; 654 case PCI_PRODUCT_AMD_CS5536_IDE: 655 case PCI_PRODUCT_AMD_PBC766_IDE: 656 case PCI_PRODUCT_AMD_PBC768_IDE: 657 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 658 break; 659 default: 660 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 661 } 662 sc->sc_apo_regbase = APO_AMD_REGBASE; 663 break; 664 case PCI_VENDOR_NVIDIA: 665 switch (sc->sc_pp->ide_product) { 666 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 667 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 668 break; 669 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 670 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 671 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 672 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 673 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 674 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 675 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 676 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 677 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 678 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 679 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 680 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 681 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 682 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 683 break; 684 } 685 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 686 break; 687 default: 688 panic("via_chip_map: unknown vendor"); 689 } 690 691 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 692 "bus-master DMA support present"); 693 pciide_mapreg_dma(sc, pa); 694 aprint_verbose("\n"); 695 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 696 if (sc->sc_dma_ok) { 697 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 698 sc->sc_wdcdev.irqack = pciide_irqack; 699 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 700 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 701 } 702 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 703 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 704 if (sc->sc_wdcdev.sc_atac.atac_set_modes == NULL) 705 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 706 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 707 if (single_channel) 708 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 709 else 710 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 711 sc->sc_wdcdev.wdc_maxdrives = 2; 712 713 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 714 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) { 715 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 716 if (interface == 0) { 717 ATADEBUG_PRINT(("via_chip_map interface == 0\n"), 718 DEBUG_PROBE); 719 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 720 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 721 } 722 } 723 724 wdc_allocate_regs(&sc->sc_wdcdev); 725 726 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 727 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 728 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 729 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 730 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 731 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 732 DEBUG_PROBE); 733 734 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 735 if ((ideconf & APO_IDECONF_ALWAYS_EN) == 0 && no_ideconf) { 736 ideconf |= APO_IDECONF_ALWAYS_EN; 737 /* 738 * VT6410 requires writing chip enable register bits to enable 739 * the channels. It can be distinguished from VT6415 because 740 * its ideconf register returns a non-zero value (contains 741 * other IDE configuration bits). 742 * 743 * VT6415 returns zero at this offset and likely uses it for 744 * a different purpose or leaves it unused. Bits are simulated 745 * without writing, until the actual offset will be known. 746 */ 747 if (ideconf != APO_IDECONF_ALWAYS_EN) { 748 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 749 ideconf); 750 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, 751 APO_IDECONF(sc)); 752 } 753 } 754 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 755 channel++) { 756 cp = &sc->pciide_channels[channel]; 757 if (pciide_chansetup(sc, channel, interface) == 0) 758 continue; 759 760 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 761 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 762 "%s channel ignored (disabled)\n", cp->name); 763 cp->ata_channel.ch_flags |= ATACH_DISABLED; 764 continue; 765 } 766 via_mapchan(pa, cp, interface, pciide_pci_intr); 767 } 768 } 769 770 static void 771 via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, 772 pcireg_t interface, int (*pci_intr)(void *)) 773 { 774 struct ata_channel *wdc_cp; 775 struct pciide_softc *sc; 776 777 wdc_cp = &cp->ata_channel; 778 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 779 780 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 781 /* native mode with irq 14/15 requested? */ 782 if (device_getprop_bool(sc->sc_wdcdev.sc_atac.atac_dev, 783 "use-compat-native-irq")) 784 via_mapregs_compat_native(pa, cp); 785 else 786 pciide_mapregs_native(pa, cp, pci_intr); 787 } else { 788 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 789 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 790 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 791 } 792 wdcattach(wdc_cp); 793 } 794 795 /* 796 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 797 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 798 * programmed to use a single native PCI irq alone. So we install an interrupt 799 * handler for each channel, as in compatibility mode. 800 */ 801 static void 802 via_mapregs_compat_native(const struct pci_attach_args *pa, 803 struct pciide_channel *cp) 804 { 805 struct ata_channel *wdc_cp; 806 struct pciide_softc *sc; 807 808 wdc_cp = &cp->ata_channel; 809 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 810 811 /* XXX prevent pciide_mapregs_native from installing a handler */ 812 if (sc->sc_pci_ih == NULL) 813 sc->sc_pci_ih = (void *)~0; 814 pciide_mapregs_native(pa, cp, NULL); 815 816 /* interrupts are fixed to 14/15, as in compatibility mode */ 817 cp->compat = 1; 818 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 819 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 820 cp->ih = pciide_machdep_compat_intr_establish( 821 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 822 pciide_compat_intr, cp); 823 if (cp->ih == NULL) { 824 #endif 825 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 826 "no compatibility interrupt for " 827 "use by %s channel\n", cp->name); 828 wdc_cp->ch_flags |= ATACH_DISABLED; 829 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 830 } 831 sc->sc_pci_ih = cp->ih; /* XXX */ 832 #endif 833 } 834 } 835 836 static void 837 via_setup_channel(struct ata_channel *chp) 838 { 839 u_int32_t udmatim_reg, datatim_reg; 840 u_int8_t idedma_ctl; 841 int mode, drive, s; 842 struct ata_drive_datas *drvp; 843 struct atac_softc *atac = chp->ch_atac; 844 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 845 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 846 #ifndef PCIIDE_AMD756_ENABLEDMA 847 int rev = PCI_REVISION( 848 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 849 #endif 850 851 idedma_ctl = 0; 852 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 853 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 854 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 855 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 856 857 /* setup DMA if needed */ 858 pciide_channel_dma_setup(cp); 859 860 for (drive = 0; drive < 2; drive++) { 861 drvp = &chp->ch_drive[drive]; 862 /* If no drive, skip */ 863 if (drvp->drive_type == ATA_DRIVET_NONE) 864 continue; 865 /* add timing values, setup DMA if needed */ 866 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 867 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) { 868 mode = drvp->PIO_mode; 869 goto pio; 870 } 871 if ((atac->atac_cap & ATAC_CAP_UDMA) && 872 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 873 /* use Ultra/DMA */ 874 s = splbio(); 875 drvp->drive_flags &= ~ATA_DRIVE_DMA; 876 splx(s); 877 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 878 APO_UDMA_EN_MTH(chp->ch_channel, drive); 879 switch (PCI_VENDOR(sc->sc_pci_id)) { 880 case PCI_VENDOR_VIATECH: 881 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 882 /* 8233a */ 883 udmatim_reg |= APO_UDMA_TIME( 884 chp->ch_channel, 885 drive, 886 via_udma133_tim[drvp->UDMA_mode]); 887 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 888 /* 686b */ 889 udmatim_reg |= APO_UDMA_TIME( 890 chp->ch_channel, 891 drive, 892 via_udma100_tim[drvp->UDMA_mode]); 893 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 894 /* 596b or 686a */ 895 udmatim_reg |= APO_UDMA_CLK66( 896 chp->ch_channel); 897 udmatim_reg |= APO_UDMA_TIME( 898 chp->ch_channel, 899 drive, 900 via_udma66_tim[drvp->UDMA_mode]); 901 } else { 902 /* 596a or 586b */ 903 udmatim_reg |= APO_UDMA_TIME( 904 chp->ch_channel, 905 drive, 906 via_udma33_tim[drvp->UDMA_mode]); 907 } 908 break; 909 case PCI_VENDOR_AMD: 910 case PCI_VENDOR_NVIDIA: 911 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 912 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 913 break; 914 } 915 /* can use PIO timings, MW DMA unused */ 916 mode = drvp->PIO_mode; 917 } else { 918 /* use Multiword DMA, but only if revision is OK */ 919 s = splbio(); 920 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 921 splx(s); 922 #ifndef PCIIDE_AMD756_ENABLEDMA 923 /* 924 * The workaround doesn't seem to be necessary 925 * with all drives, so it can be disabled by 926 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 927 * triggered. 928 */ 929 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 930 sc->sc_pp->ide_product == 931 PCI_PRODUCT_AMD_PBC756_IDE && 932 AMD756_CHIPREV_DISABLEDMA(rev)) { 933 aprint_normal( 934 "%s:%d:%d: multi-word DMA disabled due " 935 "to chip revision\n", 936 device_xname( 937 sc->sc_wdcdev.sc_atac.atac_dev), 938 chp->ch_channel, drive); 939 mode = drvp->PIO_mode; 940 s = splbio(); 941 drvp->drive_flags &= ~ATA_DRIVE_DMA; 942 splx(s); 943 goto pio; 944 } 945 #endif 946 /* mode = min(pio, dma+2) */ 947 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 948 mode = drvp->PIO_mode; 949 else 950 mode = drvp->DMA_mode + 2; 951 } 952 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 953 954 pio: /* setup PIO mode */ 955 if (mode <= 2) { 956 drvp->DMA_mode = 0; 957 drvp->PIO_mode = 0; 958 mode = 0; 959 } else { 960 drvp->PIO_mode = mode; 961 drvp->DMA_mode = mode - 2; 962 } 963 datatim_reg |= 964 APO_DATATIM_PULSE(chp->ch_channel, drive, 965 apollo_pio_set[mode]) | 966 APO_DATATIM_RECOV(chp->ch_channel, drive, 967 apollo_pio_rec[mode]); 968 } 969 if (idedma_ctl != 0) { 970 /* Add software bits in status register */ 971 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 972 idedma_ctl); 973 } 974 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 975 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 976 ATADEBUG_PRINT(("%s: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 977 __func__, 978 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 979 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 980 } 981 982 static int 983 via_sata_chip_map_common(struct pciide_softc *sc, 984 const struct pci_attach_args *cpa) 985 { 986 pcireg_t csr; 987 int maptype, ret; 988 struct pci_attach_args pac, *pa = &pac; 989 990 pac = *cpa; 991 992 if (pciide_chipen(sc, pa) == 0) 993 return 0; 994 995 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 996 "bus-master DMA support present"); 997 pciide_mapreg_dma(sc, pa); 998 aprint_verbose("\n"); 999 1000 if (sc->sc_dma_ok) { 1001 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 1002 sc->sc_wdcdev.irqack = pciide_irqack; 1003 } 1004 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1005 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1006 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1007 1008 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1009 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 1010 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1011 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1012 sc->sc_wdcdev.wdc_maxdrives = 2; 1013 1014 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1015 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1016 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1017 1018 wdc_allocate_regs(&sc->sc_wdcdev); 1019 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1020 PCI_MAPREG_START + 0x14); 1021 switch(maptype) { 1022 case PCI_MAPREG_TYPE_IO: 1023 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 1024 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 1025 NULL, &sc->sc_ba5_ss); 1026 break; 1027 case PCI_MAPREG_MEM_TYPE_32BIT: 1028 /* 1029 * Enable memory-space access if it isn't already there. 1030 */ 1031 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, 1032 PCI_COMMAND_STATUS_REG); 1033 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 && 1034 (pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) { 1035 1036 pci_conf_write(pa->pa_pc, pa->pa_tag, 1037 PCI_COMMAND_STATUS_REG, 1038 csr | PCI_COMMAND_MEM_ENABLE); 1039 } 1040 1041 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 1042 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1043 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 1044 NULL, &sc->sc_ba5_ss); 1045 break; 1046 default: 1047 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1048 "couldn't map sata regs, unsupported maptype (0x%x)\n", 1049 maptype); 1050 return 0; 1051 } 1052 if (ret != 0) { 1053 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1054 "couldn't map sata regs\n"); 1055 return 0; 1056 } 1057 return 1; 1058 } 1059 1060 static void 1061 via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa, 1062 int satareg_shift) 1063 { 1064 struct pciide_channel *cp; 1065 struct ata_channel *wdc_cp; 1066 struct wdc_regs *wdr; 1067 pcireg_t interface; 1068 int channel; 1069 1070 interface = PCI_INTERFACE(pa->pa_class); 1071 1072 if (via_sata_chip_map_common(sc, pa) == 0) 1073 return; 1074 1075 if (interface == 0) { 1076 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1077 DEBUG_PROBE); 1078 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1079 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1080 } 1081 1082 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1083 sc->sc_wdcdev.wdc_maxdrives = 1; 1084 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1085 channel++) { 1086 cp = &sc->pciide_channels[channel]; 1087 if (pciide_chansetup(sc, channel, interface) == 0) 1088 continue; 1089 wdc_cp = &cp->ata_channel; 1090 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1091 wdr->sata_iot = sc->sc_ba5_st; 1092 wdr->sata_baseioh = sc->sc_ba5_sh; 1093 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1094 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4, 1095 &wdr->sata_status) != 0) { 1096 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1097 "couldn't map channel %d sata_status regs\n", 1098 wdc_cp->ch_channel); 1099 continue; 1100 } 1101 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1102 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4, 1103 &wdr->sata_error) != 0) { 1104 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1105 "couldn't map channel %d sata_error regs\n", 1106 wdc_cp->ch_channel); 1107 continue; 1108 } 1109 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1110 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4, 1111 &wdr->sata_control) != 0) { 1112 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1113 "couldn't map channel %d sata_control regs\n", 1114 wdc_cp->ch_channel); 1115 continue; 1116 } 1117 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 1118 } 1119 } 1120 1121 static void 1122 via_sata_chip_map_6(struct pciide_softc *sc, const struct pci_attach_args *pa) 1123 { 1124 via_sata_chip_map(sc, pa, 6); 1125 } 1126 1127 static void 1128 via_sata_chip_map_7(struct pciide_softc *sc, const struct pci_attach_args *pa) 1129 { 1130 via_sata_chip_map(sc, pa, 7); 1131 } 1132 1133 static void 1134 via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 1135 { 1136 struct pciide_channel *pc; 1137 int chan, reg; 1138 bus_size_t size; 1139 1140 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 1141 PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh, 1142 NULL, &sc->sc_dma_ios) == 0); 1143 sc->sc_dmat = pa->pa_dmat; 1144 if (sc->sc_dma_ok == 0) { 1145 aprint_verbose(", but unused (couldn't map registers)"); 1146 } else { 1147 sc->sc_wdcdev.dma_arg = sc; 1148 sc->sc_wdcdev.dma_init = pciide_dma_init; 1149 sc->sc_wdcdev.dma_start = pciide_dma_start; 1150 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1151 } 1152 1153 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 1154 PCIIDE_OPTIONS_NODMA) { 1155 aprint_verbose( 1156 ", but unused (forced off by config file)"); 1157 sc->sc_dma_ok = 0; 1158 } 1159 1160 if (sc->sc_dma_ok == 0) 1161 return; 1162 1163 for (chan = 0; chan < 4; chan++) { 1164 pc = &sc->pciide_channels[chan]; 1165 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 1166 size = 4; 1167 if (size > (IDEDMA_SCH_OFFSET - reg)) 1168 size = IDEDMA_SCH_OFFSET - reg; 1169 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 1170 IDEDMA_SCH_OFFSET * chan + reg, size, 1171 &pc->dma_iohs[reg]) != 0) { 1172 sc->sc_dma_ok = 0; 1173 aprint_verbose(", but can't subregion offset " 1174 "%d size %lu", 1175 reg, (u_long)size); 1176 return; 1177 } 1178 } 1179 } 1180 } 1181 1182 static int 1183 via_vt6421_chansetup(struct pciide_softc *sc, int channel) 1184 { 1185 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1186 1187 sc->wdc_chanarray[channel] = &cp->ata_channel; 1188 1189 cp->ata_channel.ch_channel = channel; 1190 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 1191 1192 return 1; 1193 } 1194 1195 static void 1196 via_sata_chip_map_new(struct pciide_softc *sc, 1197 const struct pci_attach_args *pa) 1198 { 1199 struct pciide_channel *cp; 1200 struct ata_channel *wdc_cp; 1201 struct wdc_regs *wdr; 1202 int channel; 1203 pci_intr_handle_t intrhandle; 1204 const char *intrstr; 1205 int i; 1206 char intrbuf[PCI_INTRSTR_LEN]; 1207 1208 if (pciide_chipen(sc, pa) == 0) 1209 return; 1210 1211 sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE; 1212 1213 if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0, 1214 &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) { 1215 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1216 "couldn't map SATA regs\n"); 1217 } 1218 1219 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1220 "bus-master DMA support present"); 1221 via_vt6421_mapreg_dma(sc, pa); 1222 aprint_verbose("\n"); 1223 1224 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 1225 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 1226 if (sc->sc_dma_ok) { 1227 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 1228 sc->sc_wdcdev.irqack = pciide_irqack; 1229 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 1230 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 1231 } 1232 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 1233 1234 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1235 sc->sc_wdcdev.sc_atac.atac_nchannels = 3; 1236 sc->sc_wdcdev.wdc_maxdrives = 2; 1237 1238 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 1239 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 1240 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 1241 1242 wdc_allocate_regs(&sc->sc_wdcdev); 1243 1244 if (pci_intr_map(pa, &intrhandle) != 0) { 1245 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1246 "couldn't map native-PCI interrupt\n"); 1247 return; 1248 } 1249 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 1250 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, 1251 intrhandle, IPL_BIO, pciide_pci_intr, sc, 1252 device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); 1253 if (sc->sc_pci_ih == NULL) { 1254 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1255 "couldn't establish native-PCI interrupt"); 1256 if (intrstr != NULL) 1257 aprint_error(" at %s", intrstr); 1258 aprint_error("\n"); 1259 return; 1260 } 1261 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1262 "using %s for native-PCI interrupt\n", 1263 intrstr ? intrstr : "unknown interrupt"); 1264 1265 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1266 channel++) { 1267 cp = &sc->pciide_channels[channel]; 1268 if (via_vt6421_chansetup(sc, channel) == 0) 1269 continue; 1270 wdc_cp = &cp->ata_channel; 1271 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1272 1273 wdr->sata_iot = sc->sc_ba5_st; 1274 wdr->sata_baseioh = sc->sc_ba5_sh; 1275 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1276 (wdc_cp->ch_channel << 6) + 0x0, 4, 1277 &wdr->sata_status) != 0) { 1278 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1279 "couldn't map channel %d sata_status regs\n", 1280 wdc_cp->ch_channel); 1281 continue; 1282 } 1283 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1284 (wdc_cp->ch_channel << 6) + 0x4, 4, 1285 &wdr->sata_error) != 0) { 1286 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1287 "couldn't map channel %d sata_error regs\n", 1288 wdc_cp->ch_channel); 1289 continue; 1290 } 1291 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1292 (wdc_cp->ch_channel << 6) + 0x8, 4, 1293 &wdr->sata_control) != 0) { 1294 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1295 "couldn't map channel %d sata_control regs\n", 1296 wdc_cp->ch_channel); 1297 continue; 1298 } 1299 1300 if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel), 1301 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1302 NULL, &wdr->cmd_ios) != 0) { 1303 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1304 "couldn't map channel %d regs\n", channel); 1305 } 1306 wdr->ctl_iot = wdr->cmd_iot; 1307 for (i = 0; i < WDC_NREG; i++) { 1308 if (bus_space_subregion(wdr->cmd_iot, 1309 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1310 &wdr->cmd_iohs[i]) != 0) { 1311 aprint_error_dev( 1312 sc->sc_wdcdev.sc_atac.atac_dev, 1313 "couldn't subregion channel %d " 1314 "cmd regs\n", channel); 1315 return; 1316 } 1317 } 1318 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1319 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1320 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1321 "couldn't map channel %d ctl regs\n", channel); 1322 return; 1323 } 1324 wdc_init_shadow_regs(wdr); 1325 wdr->data32iot = wdr->cmd_iot; 1326 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1327 wdcattach(wdc_cp); 1328 } 1329 } 1330
Indexes created Sun Oct 25 00:26:45 UTC 2026