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      1 /*	$NetBSD: ingenic_coreregs.h,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014 Michael Lorenz
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef INGENIC_COREREGS_H
     30 #define INGENIC_COREREGS_H
     31 
     32 #ifdef _LOCORE
     33 #define	_(n)	__CONCAT($,n)
     34 #else
     35 #define	_(n)	n
     36 #endif
     37 
     38 /* cores status, 12 select 3 */
     39 #define CP0_CORE_CTRL	_(12), 2	/* select 2 */
     40 #define  CC_SW_RST0	__BIT(0)	/* reset core 0 */
     41 #define  CC_SW_RST1	__BIT(1)	/* reset core 1 */
     42 #define  CC_RPC0	__BIT(8)	/* dedicated reset entry core 0 */
     43 #define  CC_RPC1	__BIT(9)	/* -- || -- core 1 */
     44 #define  CC_SLEEP0M	__BIT(16)	/* mask sleep core 0 */
     45 #define  CC_SLEEP1M	__BIT(17)	/* mask sleep core 1 */
     46 
     47 /* cores status, 12 select 3 */
     48 #define CP0_CORE_STATUS	_(12), 3
     49 #define  CS_MIRQ0_P	__BIT(0)	/* mailbox IRQ for 0 pending */
     50 #define  CS_MIRQ1_P	__BIT(1)	/* || core 1 */
     51 #define  CS_IRQ0_P	__BIT(8)	/* peripheral IRQ for core 0 */
     52 #define  CS_IRQ1_P	__BIT(9)	/* || core 1 */
     53 #define  CS_SLEEP0	__BIT(16)	/* core 0 sleeping */
     54 #define  CS_SLEEP1	__BIT(17)	/* core 1 sleeping */
     55 
     56 /* cores reset entry & IRQ masks - 12 select 4 */
     57 #define CP0_CORE_REIM	_(12), 4
     58 #define  REIM_MIRQ0_M	__BIT(0)	/* allow mailbox IRQ for core 0 */
     59 #define  REIM_MIRQ1_M	__BIT(1)	/* allow mailbox IRQ for core 1 */
     60 #define  REIM_IRQ0_M	__BIT(8)	/* allow peripheral IRQ for core 0 */
     61 #define  REIM_IRQ1_M	__BIT(9)	/* allow peripheral IRQ for core 1 */
     62 #define  REIM_ENTRY_M	__BITS(31,16)	/* reset exception entry if RPCn=1 */
     63 
     64 #define CP0_SPINLOCK	_(12), 5
     65 #define CP0_SPINATOMIC	_(12), 6
     66 
     67 #define CP0_CORE0_MBOX	_(20), 0
     68 #define CP0_CORE1_MBOX	_(20), 1
     69 
     70 #endif /* INGENIC_COREREGS_H */
     71