| /src/sys/arch/cobalt/stand/boot/ |
| ns16550.c | 40 #define CSR_WRITE(base, reg, val) \
52 CSR_WRITE(com_port, com_lctl, LCR_DLAB);
54 CSR_WRITE(com_port, com_dlbl, speed);
55 CSR_WRITE(com_port, com_dlbh, speed >> 8);
57 CSR_WRITE(com_port, com_lctl, LCR_PNONE | LCR_8BITS);
58 CSR_WRITE(com_port, com_mcr, MCR_RTS | MCR_DTR);
59 CSR_WRITE(com_port, com_fifo,
61 CSR_WRITE(com_port, com_ier, 0);
74 CSR_WRITE(com_port, com_data, c);
|
| lcd.c | 44 #define CSR_WRITE(base, reg, val) \
109 CSR_WRITE(lcd_base, IREG, cmd_ddramset(HD_ROW1_ADDR + i));
110 CSR_WRITE(lcd_base, DREG, message->row1[i]);
113 CSR_WRITE(lcd_base, IREG, cmd_ddramset(HD_ROW2_ADDR + i));
114 CSR_WRITE(lcd_base, DREG, message->row2[i]);
|
| tlp.c | 52 #define CSR_WRITE(l, r, v) \
198 CSR_WRITE(l, TLP_BMR, val | BMR_RST);
200 CSR_WRITE(l, TLP_BMR, val);
206 CSR_WRITE(l, TLP_CSR13, 0);
208 CSR_WRITE(l, TLP_CSR15, SIAGEN_10BT);
209 CSR_WRITE(l, TLP_CSR14, SIATXRX_10BT);
210 CSR_WRITE(l, TLP_CSR13, SIACONN_10BT);
213 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE | SIAGEN_MD0);
215 CSR_WRITE(l, TLP_CSR15, SIAGEN_CWE);
220 CSR_WRITE(l, TLP_OMR, l->omr)
[all...] |
| /src/sys/arch/mmeye/stand/boot/ |
| com.c | 103 #define CSR_WRITE(base, reg, val) \
143 CSR_WRITE(com_port, com_lctl, LCR_DLAB);
145 CSR_WRITE(com_port, com_dlbl, speed);
146 CSR_WRITE(com_port, com_dlbh, speed >> 8);
148 CSR_WRITE(com_port, com_lctl, LCR_PNONE | LCR_8BITS);
149 CSR_WRITE(com_port, com_mcr, MCR_RTS | MCR_DTR);
150 CSR_WRITE(com_port, com_fifo,
152 CSR_WRITE(com_port, com_ier, 0);
165 CSR_WRITE(com_port, com_data, c);
|
| /src/sys/dev/ic/ |
| pca9564.c | 60 #define CSR_WRITE(sc, r, v) (*sc->sc_ios.write_byte)(sc->sc_dev, r, v)
128 CSR_WRITE(sc, PCA9564_I2CCON, control);
143 CSR_WRITE(sc, PCA9564_I2CCON, control);
177 CSR_WRITE(sc, PCA9564_I2CCON, control);
193 CSR_WRITE(sc, PCA9564_I2CCON, control);
217 CSR_WRITE(sc, PCA9564_I2CDAT, data);
220 CSR_WRITE(sc, PCA9564_I2CCON, control);
266 CSR_WRITE(sc, PCA9564_I2CDAT, byte);
269 CSR_WRITE(sc, PCA9564_I2CCON, control);
293 CSR_WRITE(sc, PCA9564_I2CCON, control)
[all...] |
| dp83932var.h | 211 #define CSR_WRITE(sc, reg, val) \
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| main.c | 46 #define CSR_WRITE(reg, val) do { \
475 CSR_WRITE(S3C2440_UART_BASE(0) + SSCOM_UTXH, c);
608 CSR_WRITE(S3C2440_GPIO_BASE + GPIO_EINTMASK, ~0);
638 CSR_WRITE(S3C2440_GPIO_BASE + 0x10 * (grp - 'A'), con);
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| sip.c | 48 #define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
149 CSR_WRITE(l, SIP_IER, 0);
150 CSR_WRITE(l, SIP_IMR, 0);
151 CSR_WRITE(l, SIP_RFCR, 0);
152 CSR_WRITE(l, SIP_CR, CR_RST);
206 CSR_WRITE(l, SIP_RFCR, 0);
207 CSR_WRITE(l, SIP_RFDR, (en[1] << 8) | en[0]);
208 CSR_WRITE(l, SIP_RFCR, 2);
209 CSR_WRITE(l, SIP_RFDR, (en[3] << 8) | en[2]);
210 CSR_WRITE(l, SIP_RFCR, 4)
[all...] |
| sme.c | 48 #define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
170 CSR_WRITE(l, TXDBASE, VTOPHYS(txd));
171 CSR_WRITE(l, RXDBASE, VTOPHYS(rxd));
175 CSR_WRITE(l, BUSMODE, 0);
176 CSR_WRITE(l, DMACCTL, DMACCTL_ST | DMACCTL_SR);
177 CSR_WRITE(l, MAC_CR, val); /* (FDX), Tx/Rx enable */
178 CSR_WRITE(l, RXPOLLD, 01); /* start receiving */
197 CSR_WRITE(l, TXPOLLD, 01); /* start transmission */
241 CSR_WRITE(l, RXPOLLD, 01); /* restart receiving */
254 CSR_WRITE(l, RXPOLLD, 01); /* necessary? *
[all...] |
| tlp.c | 48 #define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
140 CSR_WRITE(l, PAR_CSR0, PAR_SWR);
145 CSR_WRITE(l, PAR_CSR0, PAR_DEFAULTS);
148 CSR_WRITE(l, NAR_CSR6, l->omr);
149 CSR_WRITE(l, SR_CSR5, ~0);
150 CSR_WRITE(l, IER_CSR7, 0);
192 CSR_WRITE(l, TDB_CSR4, VTOPHYS(txd));
193 CSR_WRITE(l, RDB_CSR3, VTOPHYS(rxd));
196 CSR_WRITE(l, NAR_CSR6, l->omr | NAR_TEN | NAR_REN);
215 CSR_WRITE(l, TDR_CSR1, 01)
[all...] |
| wm.c | 50 #define CSR_WRITE(l, r, v) out32rb((l)->csr+(r), (v))
148 CSR_WRITE(l, WMREG_TCTL, 0);
149 CSR_WRITE(l, WMREG_RCTL, 0);
188 CSR_WRITE(l, WMREG_TDBAH, 0);
189 CSR_WRITE(l, WMREG_TDBAL, VTOPHYS(txd));
190 CSR_WRITE(l, WMREG_TDLEN, sizeof(l->txd));
191 CSR_WRITE(l, WMREG_TDH, 0);
192 CSR_WRITE(l, WMREG_TDT, 0);
193 CSR_WRITE(l, WMREG_TIDV, 64);
194 CSR_WRITE(l, WMREG_TADV, 128)
[all...] |
| /src/sys/arch/arm/sociox/ |
| sni_i2c.c | 139 #define CSR_WRITE(sc, reg, val) \
|
| if_scx.c | 546 #define CSR_WRITE(sc,off,val) \
620 CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);
629 CSR_WRITE(sc, MACDATA, val);
630 CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);
1021 CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
1022 CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
1023 CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
1024 CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
1025 CSR_WRITE(sc, TXCONF, DESCNF_LE); /* little endian */
1026 CSR_WRITE(sc, RXCONF, DESCNF_LE); /* little endian *
[all...] |
| /src/sys/arch/sandpoint/sandpoint/ |
| satmgr.c | 189 #define CSR_WRITE(t,r,v) bus_space_write_1((t)->sc_iot, (t)->sc_ioh, (r), (v))
261 CSR_WRITE(sc, IER, 0x7f); /* all but MSR */
462 CSR_WRITE(sc, THR, *msg++);
715 CSR_WRITE(sc, THR, *sc->sc_wr_ptr);
|
| /src/sys/dev/pci/ |
| if_dge.c | 367 #define CSR_WRITE(sc, reg, val) \
418 CSR_WRITE((sc), DGE_RDT, (x)); \
456 CSR_WRITE((sc), DGE_RDT, (x)); \
1373 CSR_WRITE(sc, DGE_TDT, nexttx);
1851 CSR_WRITE(sc, DGE_CTRL0, CTRL0_RST | sc->sc_ctrl0);
1869 CSR_WRITE(sc, DGE_CTRL1, CTRL1_EE_RST);
1922 CSR_WRITE(sc, DGE_TDBAH, ((uint64_t)DGE_CDTXADDR(sc, 0)) >> 32);
1923 CSR_WRITE(sc, DGE_TDBAL, DGE_CDTXADDR(sc, 0));
1924 CSR_WRITE(sc, DGE_TDLEN, sizeof(sc->sc_txdescs));
1925 CSR_WRITE(sc, DGE_TDH, 0)
[all...] |
| if_wm.c | 793 #define CSR_WRITE(sc, reg, val) \
1870 CSR_WRITE(sc, reg, regval);
1970 CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
2633 CSR_WRITE(sc, WMREG_SWSM2, reg | SWSM2_LOCK);
2652 CSR_WRITE(sc, WMREG_SWSM, reg & ~SWSM_SMBI);
2990 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
2992 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
3069 CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3083 CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
3771 CSR_WRITE(sc, WMREG_WUS, 0xffffffff); /* W1C *
[all...] |
