1 /* $NetBSD: r128_drv.h,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */ 2 3 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 4 * Created: Mon Dec 13 09:51:11 1999 by faith (at) precisioninsight.com 5 */ 6 /* 7 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 8 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 9 * All rights reserved. 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the next 19 * paragraph) shall be included in all copies or substantial portions of the 20 * Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 * 30 * Authors: 31 * Rickard E. (Rik) Faith <faith (at) valinux.com> 32 * Kevin E. Martin <martin (at) valinux.com> 33 * Gareth Hughes <gareth (at) valinux.com> 34 * Michel Dzer <daenzerm (at) student.ethz.ch> 35 */ 36 37 #ifndef __R128_DRV_H__ 38 #define __R128_DRV_H__ 39 40 #include <linux/delay.h> 41 #include <linux/io.h> 42 #include <linux/irqreturn.h> 43 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_legacy.h> 46 #include <drm/r128_drm.h> 47 48 #include "ati_pcigart.h" 49 50 /* General customization: 51 */ 52 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 53 54 #define DRIVER_NAME "r128" 55 #define DRIVER_DESC "ATI Rage 128" 56 #define DRIVER_DATE "20030725" 57 58 /* Interface history: 59 * 60 * ?? - ?? 61 * 2.4 - Add support for ycbcr textures (no new ioctls) 62 * 2.5 - Add FLIP ioctl, disable FULLSCREEN. 63 */ 64 #define DRIVER_MAJOR 2 65 #define DRIVER_MINOR 5 66 #define DRIVER_PATCHLEVEL 0 67 68 #define GET_RING_HEAD(dev_priv) R128_READ(R128_PM4_BUFFER_DL_RPTR) 69 70 typedef struct drm_r128_freelist { 71 unsigned int age; 72 struct drm_buf *buf; 73 struct drm_r128_freelist *next; 74 struct drm_r128_freelist *prev; 75 } drm_r128_freelist_t; 76 77 typedef struct drm_r128_ring_buffer { 78 u32 *start; 79 u32 *end; 80 int size; 81 int size_l2qw; 82 83 u32 tail; 84 u32 tail_mask; 85 int space; 86 87 int high_mark; 88 } drm_r128_ring_buffer_t; 89 90 typedef struct drm_r128_private { 91 drm_r128_ring_buffer_t ring; 92 drm_r128_sarea_t *sarea_priv; 93 94 int cce_mode; 95 int cce_fifo_size; 96 int cce_running; 97 98 drm_r128_freelist_t *head; 99 drm_r128_freelist_t *tail; 100 101 int usec_timeout; 102 int is_pci; 103 unsigned long cce_buffers_offset; 104 105 atomic_t idle_count; 106 107 int page_flipping; 108 int current_page; 109 u32 crtc_offset; 110 u32 crtc_offset_cntl; 111 112 atomic_t vbl_received; 113 114 u32 color_fmt; 115 unsigned int front_offset; 116 unsigned int front_pitch; 117 unsigned int back_offset; 118 unsigned int back_pitch; 119 120 u32 depth_fmt; 121 unsigned int depth_offset; 122 unsigned int depth_pitch; 123 unsigned int span_offset; 124 125 u32 front_pitch_offset_c; 126 u32 back_pitch_offset_c; 127 u32 depth_pitch_offset_c; 128 u32 span_pitch_offset_c; 129 130 drm_local_map_t *sarea; 131 drm_local_map_t *mmio; 132 drm_local_map_t *cce_ring; 133 drm_local_map_t *ring_rptr; 134 drm_local_map_t *agp_textures; 135 struct drm_ati_pcigart_info gart_info; 136 } drm_r128_private_t; 137 138 typedef struct drm_r128_buf_priv { 139 u32 age; 140 int prim; 141 int discard; 142 int dispatched; 143 drm_r128_freelist_t *list_entry; 144 } drm_r128_buf_priv_t; 145 146 extern const struct drm_ioctl_desc r128_ioctls[]; 147 extern int r128_max_ioctl; 148 149 /* r128_cce.c */ 150 extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 151 extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 152 extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 153 extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 154 extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 155 extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 156 extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 157 extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 158 159 extern int r128_cce_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv); 160 extern int r128_cce_depth(struct drm_device *dev, void *data, struct drm_file *file_priv); 161 extern int r128_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv); 162 163 extern void r128_freelist_reset(struct drm_device *dev); 164 165 extern int r128_wait_ring(drm_r128_private_t *dev_priv, int n); 166 167 extern int r128_do_cce_idle(drm_r128_private_t *dev_priv); 168 extern int r128_do_cleanup_cce(struct drm_device *dev); 169 170 extern int r128_enable_vblank(struct drm_device *dev, unsigned int pipe); 171 extern void r128_disable_vblank(struct drm_device *dev, unsigned int pipe); 172 extern u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe); 173 extern irqreturn_t r128_driver_irq_handler(int irq, void *arg); 174 extern void r128_driver_irq_preinstall(struct drm_device *dev); 175 extern int r128_driver_irq_postinstall(struct drm_device *dev); 176 extern void r128_driver_irq_uninstall(struct drm_device *dev); 177 extern void r128_driver_lastclose(struct drm_device *dev); 178 extern int r128_driver_load(struct drm_device *dev, unsigned long flags); 179 extern void r128_driver_preclose(struct drm_device *dev, 180 struct drm_file *file_priv); 181 182 extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, 183 unsigned long arg); 184 185 /* Register definitions, register access macros and drmAddMap constants 186 * for Rage 128 kernel driver. 187 */ 188 189 #define R128_AUX_SC_CNTL 0x1660 190 # define R128_AUX1_SC_EN (1 << 0) 191 # define R128_AUX1_SC_MODE_OR (0 << 1) 192 # define R128_AUX1_SC_MODE_NAND (1 << 1) 193 # define R128_AUX2_SC_EN (1 << 2) 194 # define R128_AUX2_SC_MODE_OR (0 << 3) 195 # define R128_AUX2_SC_MODE_NAND (1 << 3) 196 # define R128_AUX3_SC_EN (1 << 4) 197 # define R128_AUX3_SC_MODE_OR (0 << 5) 198 # define R128_AUX3_SC_MODE_NAND (1 << 5) 199 #define R128_AUX1_SC_LEFT 0x1664 200 #define R128_AUX1_SC_RIGHT 0x1668 201 #define R128_AUX1_SC_TOP 0x166c 202 #define R128_AUX1_SC_BOTTOM 0x1670 203 #define R128_AUX2_SC_LEFT 0x1674 204 #define R128_AUX2_SC_RIGHT 0x1678 205 #define R128_AUX2_SC_TOP 0x167c 206 #define R128_AUX2_SC_BOTTOM 0x1680 207 #define R128_AUX3_SC_LEFT 0x1684 208 #define R128_AUX3_SC_RIGHT 0x1688 209 #define R128_AUX3_SC_TOP 0x168c 210 #define R128_AUX3_SC_BOTTOM 0x1690 211 212 #define R128_BRUSH_DATA0 0x1480 213 #define R128_BUS_CNTL 0x0030 214 # define R128_BUS_MASTER_DIS (1 << 6) 215 216 #define R128_CLOCK_CNTL_INDEX 0x0008 217 #define R128_CLOCK_CNTL_DATA 0x000c 218 # define R128_PLL_WR_EN (1 << 7) 219 #define R128_CONSTANT_COLOR_C 0x1d34 220 #define R128_CRTC_OFFSET 0x0224 221 #define R128_CRTC_OFFSET_CNTL 0x0228 222 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) 223 224 #define R128_DP_GUI_MASTER_CNTL 0x146c 225 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 226 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 227 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 228 # define R128_GMC_BRUSH_NONE (15 << 4) 229 # define R128_GMC_DST_16BPP (4 << 8) 230 # define R128_GMC_DST_24BPP (5 << 8) 231 # define R128_GMC_DST_32BPP (6 << 8) 232 # define R128_GMC_DST_DATATYPE_SHIFT 8 233 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 234 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 235 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 236 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 237 # define R128_GMC_AUX_CLIP_DIS (1 << 29) 238 # define R128_GMC_WR_MSK_DIS (1 << 30) 239 # define R128_ROP3_S 0x00cc0000 240 # define R128_ROP3_P 0x00f00000 241 #define R128_DP_WRITE_MASK 0x16cc 242 #define R128_DST_PITCH_OFFSET_C 0x1c80 243 # define R128_DST_TILE (1 << 31) 244 245 #define R128_GEN_INT_CNTL 0x0040 246 # define R128_CRTC_VBLANK_INT_EN (1 << 0) 247 #define R128_GEN_INT_STATUS 0x0044 248 # define R128_CRTC_VBLANK_INT (1 << 0) 249 # define R128_CRTC_VBLANK_INT_AK (1 << 0) 250 #define R128_GEN_RESET_CNTL 0x00f0 251 # define R128_SOFT_RESET_GUI (1 << 0) 252 253 #define R128_GUI_SCRATCH_REG0 0x15e0 254 #define R128_GUI_SCRATCH_REG1 0x15e4 255 #define R128_GUI_SCRATCH_REG2 0x15e8 256 #define R128_GUI_SCRATCH_REG3 0x15ec 257 #define R128_GUI_SCRATCH_REG4 0x15f0 258 #define R128_GUI_SCRATCH_REG5 0x15f4 259 260 #define R128_GUI_STAT 0x1740 261 # define R128_GUI_FIFOCNT_MASK 0x0fff 262 # define R128_GUI_ACTIVE (1 << 31) 263 264 #define R128_MCLK_CNTL 0x000f 265 # define R128_FORCE_GCP (1 << 16) 266 # define R128_FORCE_PIPE3D_CP (1 << 17) 267 # define R128_FORCE_RCP (1 << 18) 268 269 #define R128_PC_GUI_CTLSTAT 0x1748 270 #define R128_PC_NGUI_CTLSTAT 0x0184 271 # define R128_PC_FLUSH_GUI (3 << 0) 272 # define R128_PC_RI_GUI (1 << 2) 273 # define R128_PC_FLUSH_ALL 0x00ff 274 # define R128_PC_BUSY (1 << 31) 275 276 #define R128_PCI_GART_PAGE 0x017c 277 #define R128_PRIM_TEX_CNTL_C 0x1cb0 278 279 #define R128_SCALE_3D_CNTL 0x1a00 280 #define R128_SEC_TEX_CNTL_C 0x1d00 281 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 282 #define R128_SETUP_CNTL 0x1bc4 283 #define R128_STEN_REF_MASK_C 0x1d40 284 285 #define R128_TEX_CNTL_C 0x1c9c 286 # define R128_TEX_CACHE_FLUSH (1 << 23) 287 288 #define R128_WAIT_UNTIL 0x1720 289 # define R128_EVENT_CRTC_OFFSET (1 << 0) 290 #define R128_WINDOW_XY_OFFSET 0x1bcc 291 292 /* CCE registers 293 */ 294 #define R128_PM4_BUFFER_OFFSET 0x0700 295 #define R128_PM4_BUFFER_CNTL 0x0704 296 # define R128_PM4_MASK (15 << 28) 297 # define R128_PM4_NONPM4 (0 << 28) 298 # define R128_PM4_192PIO (1 << 28) 299 # define R128_PM4_192BM (2 << 28) 300 # define R128_PM4_128PIO_64INDBM (3 << 28) 301 # define R128_PM4_128BM_64INDBM (4 << 28) 302 # define R128_PM4_64PIO_128INDBM (5 << 28) 303 # define R128_PM4_64BM_128INDBM (6 << 28) 304 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 305 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) 306 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) 307 # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) 308 309 #define R128_PM4_BUFFER_WM_CNTL 0x0708 310 # define R128_WMA_SHIFT 0 311 # define R128_WMB_SHIFT 8 312 # define R128_WMC_SHIFT 16 313 # define R128_WB_WM_SHIFT 24 314 315 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 316 #define R128_PM4_BUFFER_DL_RPTR 0x0710 317 #define R128_PM4_BUFFER_DL_WPTR 0x0714 318 # define R128_PM4_BUFFER_DL_DONE (1 << 31) 319 320 #define R128_PM4_VC_FPU_SETUP 0x071c 321 322 #define R128_PM4_IW_INDOFF 0x0738 323 #define R128_PM4_IW_INDSIZE 0x073c 324 325 #define R128_PM4_STAT 0x07b8 326 # define R128_PM4_FIFOCNT_MASK 0x0fff 327 # define R128_PM4_BUSY (1 << 16) 328 # define R128_PM4_GUI_ACTIVE (1 << 31) 329 330 #define R128_PM4_MICROCODE_ADDR 0x07d4 331 #define R128_PM4_MICROCODE_RADDR 0x07d8 332 #define R128_PM4_MICROCODE_DATAH 0x07dc 333 #define R128_PM4_MICROCODE_DATAL 0x07e0 334 335 #define R128_PM4_BUFFER_ADDR 0x07f0 336 #define R128_PM4_MICRO_CNTL 0x07fc 337 # define R128_PM4_MICRO_FREERUN (1 << 30) 338 339 #define R128_PM4_FIFO_DATA_EVEN 0x1000 340 #define R128_PM4_FIFO_DATA_ODD 0x1004 341 342 /* CCE command packets 343 */ 344 #define R128_CCE_PACKET0 0x00000000 345 #define R128_CCE_PACKET1 0x40000000 346 #define R128_CCE_PACKET2 0x80000000 347 #define R128_CCE_PACKET3 0xC0000000 348 # define R128_CNTL_HOSTDATA_BLT 0x00009400 349 # define R128_CNTL_PAINT_MULTI 0x00009A00 350 # define R128_CNTL_BITBLT_MULTI 0x00009B00 351 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 352 353 #define R128_CCE_PACKET_MASK 0xC0000000 354 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 355 #define R128_CCE_PACKET0_REG_MASK 0x000007ff 356 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff 357 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800 358 359 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 360 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 361 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 362 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 363 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 364 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 365 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 366 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 367 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 368 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 369 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 370 #define R128_CCE_VC_CNTL_NUM_SHIFT 16 371 372 #define R128_DATATYPE_VQ 0 373 #define R128_DATATYPE_CI4 1 374 #define R128_DATATYPE_CI8 2 375 #define R128_DATATYPE_ARGB1555 3 376 #define R128_DATATYPE_RGB565 4 377 #define R128_DATATYPE_RGB888 5 378 #define R128_DATATYPE_ARGB8888 6 379 #define R128_DATATYPE_RGB332 7 380 #define R128_DATATYPE_Y8 8 381 #define R128_DATATYPE_RGB8 9 382 #define R128_DATATYPE_CI16 10 383 #define R128_DATATYPE_YVYU422 11 384 #define R128_DATATYPE_VYUY422 12 385 #define R128_DATATYPE_AYUV444 14 386 #define R128_DATATYPE_ARGB4444 15 387 388 /* Constants */ 389 #define R128_AGP_OFFSET 0x02000000 390 391 #define R128_WATERMARK_L 16 392 #define R128_WATERMARK_M 8 393 #define R128_WATERMARK_N 8 394 #define R128_WATERMARK_K 128 395 396 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 397 398 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 399 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 400 #define R128_MAX_VB_AGE 0x7fffffff 401 #define R128_MAX_VB_VERTS (0xffff) 402 403 #define R128_RING_HIGH_MARK 128 404 405 #define R128_PERFORMANCE_BOXES 0 406 407 #define R128_PCIGART_TABLE_SIZE 32768 408 409 #define R128_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) 410 #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 411 #define R128_READ8(reg) readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) 412 #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 413 414 #define R128_WRITE_PLL(addr, val) \ 415 do { \ 416 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ 417 ((addr) & 0x1f) | R128_PLL_WR_EN); \ 418 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 419 } while (0) 420 421 #define CCE_PACKET0(reg, n) (R128_CCE_PACKET0 | \ 422 ((n) << 16) | ((reg) >> 2)) 423 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \ 424 (((reg1) >> 2) << 11) | ((reg0) >> 2)) 425 #define CCE_PACKET2() (R128_CCE_PACKET2) 426 #define CCE_PACKET3(pkt, n) (R128_CCE_PACKET3 | \ 427 (pkt) | ((n) << 16)) 428 429 static __inline__ void r128_update_ring_snapshot(drm_r128_private_t *dev_priv) 430 { 431 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 432 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); 433 if (ring->space <= 0) 434 ring->space += ring->size; 435 } 436 437 /* ================================================================ 438 * Misc helper macros 439 */ 440 441 #define DEV_INIT_TEST_WITH_RETURN(_dev_priv) \ 442 do { \ 443 if (!_dev_priv) { \ 444 DRM_ERROR("called with no initialization\n"); \ 445 return -EINVAL; \ 446 } \ 447 } while (0) 448 449 #define RING_SPACE_TEST_WITH_RETURN(dev_priv) \ 450 do { \ 451 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 452 if (ring->space < ring->high_mark) { \ 453 for (i = 0 ; i < dev_priv->usec_timeout ; i++) { \ 454 r128_update_ring_snapshot(dev_priv); \ 455 if (ring->space >= ring->high_mark) \ 456 goto __ring_space_done; \ 457 udelay(1); \ 458 } \ 459 DRM_ERROR("ring space check failed!\n"); \ 460 return -EBUSY; \ 461 } \ 462 __ring_space_done: \ 463 ; \ 464 } while (0) 465 466 #define VB_AGE_TEST_WITH_RETURN(dev_priv) \ 467 do { \ 468 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 469 if (sarea_priv->last_dispatch >= R128_MAX_VB_AGE) { \ 470 int __ret = r128_do_cce_idle(dev_priv); \ 471 if (__ret) \ 472 return __ret; \ 473 sarea_priv->last_dispatch = 0; \ 474 r128_freelist_reset(dev); \ 475 } \ 476 } while (0) 477 478 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ 479 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \ 480 OUT_RING(R128_EVENT_CRTC_OFFSET); \ 481 } while (0) 482 483 /* ================================================================ 484 * Ring control 485 */ 486 487 #define R128_VERBOSE 0 488 489 #define RING_LOCALS \ 490 int write, _nr; unsigned int tail_mask; volatile u32 *ring; 491 492 #define BEGIN_RING(n) do { \ 493 if (R128_VERBOSE) \ 494 DRM_INFO("BEGIN_RING(%d)\n", (n)); \ 495 if (dev_priv->ring.space <= (n) * sizeof(u32)) { \ 496 COMMIT_RING(); \ 497 r128_wait_ring(dev_priv, (n) * sizeof(u32)); \ 498 } \ 499 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 500 ring = dev_priv->ring.start; \ 501 write = dev_priv->ring.tail; \ 502 tail_mask = dev_priv->ring.tail_mask; \ 503 } while (0) 504 505 /* You can set this to zero if you want. If the card locks up, you'll 506 * need to keep this set. It works around a bug in early revs of the 507 * Rage 128 chipset, where the CCE would read 32 dwords past the end of 508 * the ring buffer before wrapping around. 509 */ 510 #define R128_BROKEN_CCE 1 511 512 #define ADVANCE_RING() do { \ 513 if (R128_VERBOSE) \ 514 DRM_INFO("ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 515 write, dev_priv->ring.tail); \ 516 if (R128_BROKEN_CCE && write < 32) \ 517 memcpy(dev_priv->ring.end, \ 518 dev_priv->ring.start, \ 519 write * sizeof(u32)); \ 520 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) \ 521 DRM_ERROR( \ 522 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 523 ((dev_priv->ring.tail + _nr) & tail_mask), \ 524 write, __LINE__); \ 525 else \ 526 dev_priv->ring.tail = write; \ 527 } while (0) 528 529 #define COMMIT_RING() do { \ 530 if (R128_VERBOSE) \ 531 DRM_INFO("COMMIT_RING() tail=0x%06x\n", \ 532 dev_priv->ring.tail); \ 533 mb(); \ 534 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail); \ 535 R128_READ(R128_PM4_BUFFER_DL_WPTR); \ 536 } while (0) 537 538 #define OUT_RING(x) do { \ 539 if (R128_VERBOSE) \ 540 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \ 541 (unsigned int)(x), write); \ 542 ring[write++] = cpu_to_le32(x); \ 543 write &= tail_mask; \ 544 } while (0) 545 546 #endif /* __R128_DRV_H__ */ 547
Indexes created Wed Oct 01 19:09:53 GMT 2025