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      1 /*	$NetBSD: ti-dp83867.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Device Tree constants for the Texas Instruments DP83867 PHY
      6  *
      7  * Author: Dan Murphy <dmurphy (at) ti.com>
      8  *
      9  * Copyright:   (C) 2015 Texas Instruments, Inc.
     10  */
     11 
     12 #ifndef _DT_BINDINGS_TI_DP83867_H
     13 #define _DT_BINDINGS_TI_DP83867_H
     14 
     15 /* PHY CTRL bits */
     16 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
     17 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
     18 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
     19 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
     20 
     21 /* RGMIIDCTL internal delay for rx and tx */
     22 #define	DP83867_RGMIIDCTL_250_PS	0x0
     23 #define	DP83867_RGMIIDCTL_500_PS	0x1
     24 #define	DP83867_RGMIIDCTL_750_PS	0x2
     25 #define	DP83867_RGMIIDCTL_1_NS		0x3
     26 #define	DP83867_RGMIIDCTL_1_25_NS	0x4
     27 #define	DP83867_RGMIIDCTL_1_50_NS	0x5
     28 #define	DP83867_RGMIIDCTL_1_75_NS	0x6
     29 #define	DP83867_RGMIIDCTL_2_00_NS	0x7
     30 #define	DP83867_RGMIIDCTL_2_25_NS	0x8
     31 #define	DP83867_RGMIIDCTL_2_50_NS	0x9
     32 #define	DP83867_RGMIIDCTL_2_75_NS	0xa
     33 #define	DP83867_RGMIIDCTL_3_00_NS	0xb
     34 #define	DP83867_RGMIIDCTL_3_25_NS	0xc
     35 #define	DP83867_RGMIIDCTL_3_50_NS	0xd
     36 #define	DP83867_RGMIIDCTL_3_75_NS	0xe
     37 #define	DP83867_RGMIIDCTL_4_00_NS	0xf
     38 
     39 /* IO_MUX_CFG - Clock output selection */
     40 #define DP83867_CLK_O_SEL_CHN_A_RCLK		0x0
     41 #define DP83867_CLK_O_SEL_CHN_B_RCLK		0x1
     42 #define DP83867_CLK_O_SEL_CHN_C_RCLK		0x2
     43 #define DP83867_CLK_O_SEL_CHN_D_RCLK		0x3
     44 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
     45 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
     46 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
     47 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
     48 #define DP83867_CLK_O_SEL_CHN_A_TCLK		0x8
     49 #define DP83867_CLK_O_SEL_CHN_B_TCLK		0x9
     50 #define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
     51 #define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
     52 #define DP83867_CLK_O_SEL_REF_CLK		0xC
     53 /* Special flag to indicate clock should be off */
     54 #define DP83867_CLK_O_SEL_OFF			0xFFFFFFFF
     55 #endif
     56