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    Searched defs:HHI_SYS_PLL_CNTL (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxbb_clkc.c 60 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0)
96 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
97 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
98 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
100 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
101 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
105 HHI_SYS_PLL_CNTL, /* reg */
meson8b_clkc.c 67 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0)
123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL);
165 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl);
170 } while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0);
185 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
186 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
187 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
189 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
190 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
195 HHI_SYS_PLL_CNTL, /* reg *
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