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      1 /*	$NetBSD: imx8mq-clock.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright 2016 Freescale Semiconductor, Inc.
      6  * Copyright 2017 NXP
      7  */
      8 
      9 #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
     10 #define __DT_BINDINGS_CLOCK_IMX8MQ_H
     11 
     12 #define IMX8MQ_CLK_DUMMY		0
     13 #define IMX8MQ_CLK_32K			1
     14 #define IMX8MQ_CLK_25M			2
     15 #define IMX8MQ_CLK_27M			3
     16 #define IMX8MQ_CLK_EXT1			4
     17 #define IMX8MQ_CLK_EXT2			5
     18 #define IMX8MQ_CLK_EXT3			6
     19 #define IMX8MQ_CLK_EXT4			7
     20 
     21 /* ANAMIX PLL clocks */
     22 /* FRAC PLLs */
     23 /* ARM PLL */
     24 #define IMX8MQ_ARM_PLL_REF_SEL		8
     25 #define IMX8MQ_ARM_PLL_REF_DIV		9
     26 #define IMX8MQ_ARM_PLL			10
     27 #define IMX8MQ_ARM_PLL_BYPASS		11
     28 #define IMX8MQ_ARM_PLL_OUT		12
     29 
     30 /* GPU PLL */
     31 #define IMX8MQ_GPU_PLL_REF_SEL		13
     32 #define IMX8MQ_GPU_PLL_REF_DIV		14
     33 #define IMX8MQ_GPU_PLL			15
     34 #define IMX8MQ_GPU_PLL_BYPASS		16
     35 #define IMX8MQ_GPU_PLL_OUT		17
     36 
     37 /* VPU PLL */
     38 #define IMX8MQ_VPU_PLL_REF_SEL		18
     39 #define IMX8MQ_VPU_PLL_REF_DIV		19
     40 #define IMX8MQ_VPU_PLL			20
     41 #define IMX8MQ_VPU_PLL_BYPASS		21
     42 #define IMX8MQ_VPU_PLL_OUT		22
     43 
     44 /* AUDIO PLL1 */
     45 #define IMX8MQ_AUDIO_PLL1_REF_SEL	23
     46 #define IMX8MQ_AUDIO_PLL1_REF_DIV	24
     47 #define IMX8MQ_AUDIO_PLL1		25
     48 #define IMX8MQ_AUDIO_PLL1_BYPASS	26
     49 #define IMX8MQ_AUDIO_PLL1_OUT		27
     50 
     51 /* AUDIO PLL2 */
     52 #define IMX8MQ_AUDIO_PLL2_REF_SEL	28
     53 #define IMX8MQ_AUDIO_PLL2_REF_DIV	29
     54 #define IMX8MQ_AUDIO_PLL2		30
     55 #define IMX8MQ_AUDIO_PLL2_BYPASS	31
     56 #define IMX8MQ_AUDIO_PLL2_OUT		32
     57 
     58 /* VIDEO PLL1 */
     59 #define IMX8MQ_VIDEO_PLL1_REF_SEL	33
     60 #define IMX8MQ_VIDEO_PLL1_REF_DIV	34
     61 #define IMX8MQ_VIDEO_PLL1		35
     62 #define IMX8MQ_VIDEO_PLL1_BYPASS	36
     63 #define IMX8MQ_VIDEO_PLL1_OUT		37
     64 
     65 /* SYS1 PLL */
     66 #define IMX8MQ_SYS1_PLL1_REF_SEL	38
     67 #define IMX8MQ_SYS1_PLL1_REF_DIV	39
     68 #define IMX8MQ_SYS1_PLL1		40
     69 #define IMX8MQ_SYS1_PLL1_OUT		41
     70 #define IMX8MQ_SYS1_PLL1_OUT_DIV	42
     71 #define IMX8MQ_SYS1_PLL2		43
     72 #define IMX8MQ_SYS1_PLL2_DIV		44
     73 #define IMX8MQ_SYS1_PLL2_OUT		45
     74 
     75 /* SYS2 PLL */
     76 #define IMX8MQ_SYS2_PLL1_REF_SEL	46
     77 #define IMX8MQ_SYS2_PLL1_REF_DIV	47
     78 #define IMX8MQ_SYS2_PLL1		48
     79 #define IMX8MQ_SYS2_PLL1_OUT		49
     80 #define IMX8MQ_SYS2_PLL1_OUT_DIV	50
     81 #define IMX8MQ_SYS2_PLL2		51
     82 #define IMX8MQ_SYS2_PLL2_DIV		52
     83 #define IMX8MQ_SYS2_PLL2_OUT		53
     84 
     85 /* SYS3 PLL */
     86 #define IMX8MQ_SYS3_PLL1_REF_SEL	54
     87 #define IMX8MQ_SYS3_PLL1_REF_DIV	55
     88 #define IMX8MQ_SYS3_PLL1		56
     89 #define IMX8MQ_SYS3_PLL1_OUT		57
     90 #define IMX8MQ_SYS3_PLL1_OUT_DIV	58
     91 #define IMX8MQ_SYS3_PLL2		59
     92 #define IMX8MQ_SYS3_PLL2_DIV		60
     93 #define IMX8MQ_SYS3_PLL2_OUT		61
     94 
     95 /* DRAM PLL */
     96 #define IMX8MQ_DRAM_PLL1_REF_SEL	62
     97 #define IMX8MQ_DRAM_PLL1_REF_DIV	63
     98 #define IMX8MQ_DRAM_PLL1		64
     99 #define IMX8MQ_DRAM_PLL1_OUT		65
    100 #define IMX8MQ_DRAM_PLL1_OUT_DIV	66
    101 #define IMX8MQ_DRAM_PLL2		67
    102 #define IMX8MQ_DRAM_PLL2_DIV		68
    103 #define IMX8MQ_DRAM_PLL2_OUT		69
    104 
    105 /* SYS PLL DIV */
    106 #define IMX8MQ_SYS1_PLL_40M		70
    107 #define IMX8MQ_SYS1_PLL_80M		71
    108 #define IMX8MQ_SYS1_PLL_100M		72
    109 #define IMX8MQ_SYS1_PLL_133M		73
    110 #define IMX8MQ_SYS1_PLL_160M		74
    111 #define IMX8MQ_SYS1_PLL_200M		75
    112 #define IMX8MQ_SYS1_PLL_266M		76
    113 #define IMX8MQ_SYS1_PLL_400M		77
    114 #define IMX8MQ_SYS1_PLL_800M		78
    115 
    116 #define IMX8MQ_SYS2_PLL_50M		79
    117 #define IMX8MQ_SYS2_PLL_100M		80
    118 #define IMX8MQ_SYS2_PLL_125M		81
    119 #define IMX8MQ_SYS2_PLL_166M		82
    120 #define IMX8MQ_SYS2_PLL_200M		83
    121 #define IMX8MQ_SYS2_PLL_250M		84
    122 #define IMX8MQ_SYS2_PLL_333M		85
    123 #define IMX8MQ_SYS2_PLL_500M		86
    124 #define IMX8MQ_SYS2_PLL_1000M		87
    125 
    126 /* CCM ROOT clocks */
    127 /* A53 */
    128 #define IMX8MQ_CLK_A53_SRC		88
    129 #define IMX8MQ_CLK_A53_CG		89
    130 #define IMX8MQ_CLK_A53_DIV		90
    131 /* M4 */
    132 #define IMX8MQ_CLK_M4_SRC		91
    133 #define IMX8MQ_CLK_M4_CG		92
    134 #define IMX8MQ_CLK_M4_DIV		93
    135 /* VPU */
    136 #define IMX8MQ_CLK_VPU_SRC		94
    137 #define IMX8MQ_CLK_VPU_CG		95
    138 #define IMX8MQ_CLK_VPU_DIV		96
    139 /* GPU CORE */
    140 #define IMX8MQ_CLK_GPU_CORE_SRC		97
    141 #define IMX8MQ_CLK_GPU_CORE_CG		98
    142 #define IMX8MQ_CLK_GPU_CORE_DIV		99
    143 /* GPU SHADER */
    144 #define IMX8MQ_CLK_GPU_SHADER_SRC	100
    145 #define IMX8MQ_CLK_GPU_SHADER_CG	101
    146 #define IMX8MQ_CLK_GPU_SHADER_DIV	102
    147 
    148 /* BUS TYPE */
    149 /* MAIN AXI */
    150 #define IMX8MQ_CLK_MAIN_AXI		103
    151 /* ENET AXI */
    152 #define IMX8MQ_CLK_ENET_AXI		104
    153 /* NAND_USDHC_BUS */
    154 #define IMX8MQ_CLK_NAND_USDHC_BUS	105
    155 /* VPU BUS */
    156 #define IMX8MQ_CLK_VPU_BUS		106
    157 /* DISP_AXI */
    158 #define IMX8MQ_CLK_DISP_AXI		107
    159 /* DISP APB */
    160 #define IMX8MQ_CLK_DISP_APB		108
    161 /* DISP RTRM */
    162 #define IMX8MQ_CLK_DISP_RTRM		109
    163 /* USB_BUS */
    164 #define IMX8MQ_CLK_USB_BUS		110
    165 /* GPU_AXI */
    166 #define IMX8MQ_CLK_GPU_AXI		111
    167 /* GPU_AHB */
    168 #define IMX8MQ_CLK_GPU_AHB		112
    169 /* NOC */
    170 #define IMX8MQ_CLK_NOC			113
    171 /* NOC_APB */
    172 #define IMX8MQ_CLK_NOC_APB		115
    173 
    174 /* AHB */
    175 #define IMX8MQ_CLK_AHB			116
    176 /* AUDIO AHB */
    177 #define IMX8MQ_CLK_AUDIO_AHB		117
    178 
    179 /* DRAM_ALT */
    180 #define IMX8MQ_CLK_DRAM_ALT		118
    181 /* DRAM APB */
    182 #define IMX8MQ_CLK_DRAM_APB		119
    183 /* VPU_G1 */
    184 #define IMX8MQ_CLK_VPU_G1		120
    185 /* VPU_G2 */
    186 #define IMX8MQ_CLK_VPU_G2		121
    187 /* DISP_DTRC */
    188 #define IMX8MQ_CLK_DISP_DTRC		122
    189 /* DISP_DC8000 */
    190 #define IMX8MQ_CLK_DISP_DC8000		123
    191 /* PCIE_CTRL */
    192 #define IMX8MQ_CLK_PCIE1_CTRL		124
    193 /* PCIE_PHY */
    194 #define IMX8MQ_CLK_PCIE1_PHY		125
    195 /* PCIE_AUX */
    196 #define IMX8MQ_CLK_PCIE1_AUX		126
    197 /* DC_PIXEL */
    198 #define IMX8MQ_CLK_DC_PIXEL		127
    199 /* LCDIF_PIXEL */
    200 #define IMX8MQ_CLK_LCDIF_PIXEL		128
    201 /* SAI1~6 */
    202 #define IMX8MQ_CLK_SAI1			129
    203 
    204 #define IMX8MQ_CLK_SAI2			130
    205 
    206 #define IMX8MQ_CLK_SAI3			131
    207 
    208 #define IMX8MQ_CLK_SAI4			132
    209 
    210 #define IMX8MQ_CLK_SAI5			133
    211 
    212 #define IMX8MQ_CLK_SAI6			134
    213 /* SPDIF1 */
    214 #define IMX8MQ_CLK_SPDIF1		135
    215 /* SPDIF2 */
    216 #define IMX8MQ_CLK_SPDIF2		136
    217 /* ENET_REF */
    218 #define IMX8MQ_CLK_ENET_REF		137
    219 /* ENET_TIMER */
    220 #define IMX8MQ_CLK_ENET_TIMER		138
    221 /* ENET_PHY */
    222 #define IMX8MQ_CLK_ENET_PHY_REF		139
    223 /* NAND */
    224 #define IMX8MQ_CLK_NAND			140
    225 /* QSPI */
    226 #define IMX8MQ_CLK_QSPI			141
    227 /* USDHC1 */
    228 #define IMX8MQ_CLK_USDHC1		142
    229 /* USDHC2 */
    230 #define IMX8MQ_CLK_USDHC2		143
    231 /* I2C1 */
    232 #define IMX8MQ_CLK_I2C1			144
    233 /* I2C2 */
    234 #define IMX8MQ_CLK_I2C2			145
    235 /* I2C3 */
    236 #define IMX8MQ_CLK_I2C3			146
    237 /* I2C4 */
    238 #define IMX8MQ_CLK_I2C4			147
    239 /* UART1 */
    240 #define IMX8MQ_CLK_UART1		148
    241 /* UART2 */
    242 #define IMX8MQ_CLK_UART2		149
    243 /* UART3 */
    244 #define IMX8MQ_CLK_UART3		150
    245 /* UART4 */
    246 #define IMX8MQ_CLK_UART4		151
    247 /* USB_CORE_REF */
    248 #define IMX8MQ_CLK_USB_CORE_REF		152
    249 /* USB_PHY_REF */
    250 #define IMX8MQ_CLK_USB_PHY_REF		153
    251 /* ECSPI1 */
    252 #define IMX8MQ_CLK_ECSPI1		154
    253 /* ECSPI2 */
    254 #define IMX8MQ_CLK_ECSPI2		155
    255 /* PWM1 */
    256 #define IMX8MQ_CLK_PWM1			156
    257 /* PWM2 */
    258 #define IMX8MQ_CLK_PWM2			157
    259 /* PWM3 */
    260 #define IMX8MQ_CLK_PWM3			158
    261 /* PWM4 */
    262 #define IMX8MQ_CLK_PWM4			159
    263 /* GPT1 */
    264 #define IMX8MQ_CLK_GPT1			160
    265 /* WDOG */
    266 #define IMX8MQ_CLK_WDOG			161
    267 /* WRCLK */
    268 #define IMX8MQ_CLK_WRCLK		162
    269 /* DSI_CORE */
    270 #define IMX8MQ_CLK_DSI_CORE		163
    271 /* DSI_PHY */
    272 #define IMX8MQ_CLK_DSI_PHY_REF		164
    273 /* DSI_DBI */
    274 #define IMX8MQ_CLK_DSI_DBI		165
    275 /*DSI_ESC */
    276 #define IMX8MQ_CLK_DSI_ESC		166
    277 /* CSI1_CORE */
    278 #define IMX8MQ_CLK_CSI1_CORE		167
    279 /* CSI1_PHY */
    280 #define IMX8MQ_CLK_CSI1_PHY_REF		168
    281 /* CSI_ESC */
    282 #define IMX8MQ_CLK_CSI1_ESC		169
    283 /* CSI2_CORE */
    284 #define IMX8MQ_CLK_CSI2_CORE		170
    285 /* CSI2_PHY */
    286 #define IMX8MQ_CLK_CSI2_PHY_REF		171
    287 /* CSI2_ESC */
    288 #define IMX8MQ_CLK_CSI2_ESC		172
    289 /* PCIE2_CTRL */
    290 #define IMX8MQ_CLK_PCIE2_CTRL		173
    291 /* PCIE2_PHY */
    292 #define IMX8MQ_CLK_PCIE2_PHY		174
    293 /* PCIE2_AUX */
    294 #define IMX8MQ_CLK_PCIE2_AUX		175
    295 /* ECSPI3 */
    296 #define IMX8MQ_CLK_ECSPI3		176
    297 
    298 /* CCGR clocks */
    299 #define IMX8MQ_CLK_A53_ROOT			177
    300 #define IMX8MQ_CLK_DRAM_ROOT			178
    301 #define IMX8MQ_CLK_ECSPI1_ROOT			179
    302 #define IMX8MQ_CLK_ECSPI2_ROOT			180
    303 #define IMX8MQ_CLK_ECSPI3_ROOT			181
    304 #define IMX8MQ_CLK_ENET1_ROOT			182
    305 #define IMX8MQ_CLK_GPT1_ROOT			183
    306 #define IMX8MQ_CLK_I2C1_ROOT			184
    307 #define IMX8MQ_CLK_I2C2_ROOT			185
    308 #define IMX8MQ_CLK_I2C3_ROOT			186
    309 #define IMX8MQ_CLK_I2C4_ROOT			187
    310 #define IMX8MQ_CLK_M4_ROOT			188
    311 #define IMX8MQ_CLK_PCIE1_ROOT			189
    312 #define IMX8MQ_CLK_PCIE2_ROOT			190
    313 #define IMX8MQ_CLK_PWM1_ROOT			191
    314 #define IMX8MQ_CLK_PWM2_ROOT			192
    315 #define IMX8MQ_CLK_PWM3_ROOT			193
    316 #define IMX8MQ_CLK_PWM4_ROOT			194
    317 #define IMX8MQ_CLK_QSPI_ROOT			195
    318 #define IMX8MQ_CLK_SAI1_ROOT			196
    319 #define IMX8MQ_CLK_SAI2_ROOT			197
    320 #define IMX8MQ_CLK_SAI3_ROOT			198
    321 #define IMX8MQ_CLK_SAI4_ROOT			199
    322 #define IMX8MQ_CLK_SAI5_ROOT			200
    323 #define IMX8MQ_CLK_SAI6_ROOT			201
    324 #define IMX8MQ_CLK_UART1_ROOT			202
    325 #define IMX8MQ_CLK_UART2_ROOT			203
    326 #define IMX8MQ_CLK_UART3_ROOT			204
    327 #define IMX8MQ_CLK_UART4_ROOT			205
    328 #define IMX8MQ_CLK_USB1_CTRL_ROOT		206
    329 #define IMX8MQ_CLK_USB2_CTRL_ROOT		207
    330 #define IMX8MQ_CLK_USB1_PHY_ROOT		208
    331 #define IMX8MQ_CLK_USB2_PHY_ROOT		209
    332 #define IMX8MQ_CLK_USDHC1_ROOT			210
    333 #define IMX8MQ_CLK_USDHC2_ROOT			211
    334 #define IMX8MQ_CLK_WDOG1_ROOT			212
    335 #define IMX8MQ_CLK_WDOG2_ROOT			213
    336 #define IMX8MQ_CLK_WDOG3_ROOT			214
    337 #define IMX8MQ_CLK_GPU_ROOT			215
    338 #define IMX8MQ_CLK_HEVC_ROOT			216
    339 #define IMX8MQ_CLK_AVC_ROOT			217
    340 #define IMX8MQ_CLK_VP9_ROOT			218
    341 #define IMX8MQ_CLK_HEVC_INTER_ROOT		219
    342 #define IMX8MQ_CLK_DISP_ROOT			220
    343 #define IMX8MQ_CLK_HDMI_ROOT			221
    344 #define IMX8MQ_CLK_HDMI_PHY_ROOT		222
    345 #define IMX8MQ_CLK_VPU_DEC_ROOT			223
    346 #define IMX8MQ_CLK_CSI1_ROOT			224
    347 #define IMX8MQ_CLK_CSI2_ROOT			225
    348 #define IMX8MQ_CLK_RAWNAND_ROOT			226
    349 #define IMX8MQ_CLK_SDMA1_ROOT			227
    350 #define IMX8MQ_CLK_SDMA2_ROOT			228
    351 #define IMX8MQ_CLK_VPU_G1_ROOT			229
    352 #define IMX8MQ_CLK_VPU_G2_ROOT			230
    353 
    354 /* SCCG PLL GATE */
    355 #define IMX8MQ_SYS1_PLL_OUT			231
    356 #define IMX8MQ_SYS2_PLL_OUT			232
    357 #define IMX8MQ_SYS3_PLL_OUT			233
    358 #define IMX8MQ_DRAM_PLL_OUT			234
    359 
    360 #define IMX8MQ_GPT_3M_CLK			235
    361 
    362 #define IMX8MQ_CLK_IPG_ROOT			236
    363 #define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
    364 #define IMX8MQ_CLK_SAI1_IPG			238
    365 #define IMX8MQ_CLK_SAI2_IPG			239
    366 #define IMX8MQ_CLK_SAI3_IPG			240
    367 #define IMX8MQ_CLK_SAI4_IPG			241
    368 #define IMX8MQ_CLK_SAI5_IPG			242
    369 #define IMX8MQ_CLK_SAI6_IPG			243
    370 
    371 /* DSI AHB/IPG clocks */
    372 /* rxesc clock */
    373 #define IMX8MQ_CLK_DSI_AHB			244
    374 /* txesc clock */
    375 #define IMX8MQ_CLK_DSI_IPG_DIV                  245
    376 
    377 #define IMX8MQ_CLK_TMU_ROOT			246
    378 
    379 /* Display root clocks */
    380 #define IMX8MQ_CLK_DISP_AXI_ROOT		247
    381 #define IMX8MQ_CLK_DISP_APB_ROOT		248
    382 #define IMX8MQ_CLK_DISP_RTRM_ROOT		249
    383 
    384 #define IMX8MQ_CLK_OCOTP_ROOT			250
    385 
    386 #define IMX8MQ_CLK_DRAM_ALT_ROOT		251
    387 #define IMX8MQ_CLK_DRAM_CORE			252
    388 
    389 #define IMX8MQ_CLK_MU_ROOT			253
    390 #define IMX8MQ_VIDEO2_PLL_OUT			254
    391 
    392 #define IMX8MQ_CLK_CLKO2			255
    393 
    394 #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
    395 
    396 #define IMX8MQ_CLK_CLKO1			257
    397 #define IMX8MQ_CLK_ARM				258
    398 
    399 #define IMX8MQ_CLK_GPIO1_ROOT			259
    400 #define IMX8MQ_CLK_GPIO2_ROOT			260
    401 #define IMX8MQ_CLK_GPIO3_ROOT			261
    402 #define IMX8MQ_CLK_GPIO4_ROOT			262
    403 #define IMX8MQ_CLK_GPIO5_ROOT			263
    404 
    405 #define IMX8MQ_CLK_SNVS_ROOT			264
    406 #define IMX8MQ_CLK_GIC				265
    407 
    408 #define IMX8MQ_VIDEO2_PLL1_REF_SEL		266
    409 
    410 #define IMX8MQ_CLK_GPU_CORE			285
    411 #define IMX8MQ_CLK_GPU_SHADER			286
    412 #define IMX8MQ_CLK_M4_CORE			287
    413 #define IMX8MQ_CLK_VPU_CORE			288
    414 
    415 #define IMX8MQ_CLK_A53_CORE			289
    416 
    417 #define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
    418 #define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
    419 #define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
    420 #define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
    421 #define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
    422 #define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
    423 #define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
    424 #define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
    425 #define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
    426 #define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
    427 #define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
    428 #define IMX8MQ_CLK_MON_SEL			301
    429 #define IMX8MQ_CLK_MON_CLK2_OUT			302
    430 
    431 #define IMX8MQ_CLK_END				303
    432 
    433 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
    434