1 /* $NetBSD: imx8-clock.h,v 1.1.1.3 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ */ 4 /* 5 * Copyright 2018 NXP 6 * Dong Aisheng <aisheng.dong (at) nxp.com> 7 */ 8 9 #ifndef __DT_BINDINGS_CLOCK_IMX_H 10 #define __DT_BINDINGS_CLOCK_IMX_H 11 12 /* LPCG clocks */ 13 14 /* LSIO SS LPCG */ 15 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 16 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 17 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 18 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 19 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 20 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 21 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 22 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 23 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 24 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 25 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 26 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 27 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 28 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 29 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 30 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 31 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 32 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 33 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 34 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 35 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 36 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 37 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 38 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 39 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 40 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 41 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 42 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 43 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 44 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 45 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 46 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 47 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 48 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 49 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 50 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 51 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 52 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 53 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 54 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 55 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 56 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 57 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 58 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 59 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 60 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 61 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 62 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 63 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 64 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 65 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 66 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 67 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 68 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 69 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 70 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 71 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 72 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 73 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 74 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 75 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 76 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 77 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 78 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 79 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 80 #define IMX_LSIO_LPCG_FSPI0_HCLK 65 81 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 82 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 83 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 84 #define IMX_LSIO_LPCG_FSPI1_HCLK 69 85 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 86 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 87 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 88 89 #define IMX_LSIO_LPCG_CLK_END 73 90 91 /* Connectivity SS LPCG */ 92 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 93 #define IMX_CONN_LPCG_SDHC0_PER_CLK 1 94 #define IMX_CONN_LPCG_SDHC0_HCLK 2 95 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 96 #define IMX_CONN_LPCG_SDHC1_PER_CLK 4 97 #define IMX_CONN_LPCG_SDHC1_HCLK 5 98 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 99 #define IMX_CONN_LPCG_SDHC2_PER_CLK 7 100 #define IMX_CONN_LPCG_SDHC2_HCLK 8 101 #define IMX_CONN_LPCG_GPMI_APB_CLK 9 102 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 103 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 104 #define IMX_CONN_LPCG_GPMI_BCH_CLK 12 105 #define IMX_CONN_LPCG_APBHDMA_CLK 13 106 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 107 #define IMX_CONN_LPCG_ENET0_TX_CLK 15 108 #define IMX_CONN_LPCG_ENET0_AHB_CLK 16 109 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 110 #define IMX_CONN_LPCG_ENET0_IPG_CLK 18 111 112 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 113 #define IMX_CONN_LPCG_ENET1_TX_CLK 20 114 #define IMX_CONN_LPCG_ENET1_AHB_CLK 21 115 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 116 #define IMX_CONN_LPCG_ENET1_IPG_CLK 23 117 118 #define IMX_CONN_LPCG_CLK_END 24 119 120 /* ADMA SS LPCG */ 121 #define IMX_ADMA_LPCG_UART0_IPG_CLK 0 122 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 123 #define IMX_ADMA_LPCG_UART1_IPG_CLK 2 124 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 125 #define IMX_ADMA_LPCG_UART2_IPG_CLK 4 126 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 127 #define IMX_ADMA_LPCG_UART3_IPG_CLK 6 128 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 129 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 130 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 131 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 132 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 133 #define IMX_ADMA_LPCG_SPI0_CLK 12 134 #define IMX_ADMA_LPCG_SPI1_CLK 13 135 #define IMX_ADMA_LPCG_SPI2_CLK 14 136 #define IMX_ADMA_LPCG_SPI3_CLK 15 137 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 138 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 139 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 140 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 141 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 142 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 143 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 144 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 145 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 146 #define IMX_ADMA_LPCG_I2C0_CLK 25 147 #define IMX_ADMA_LPCG_I2C1_CLK 26 148 #define IMX_ADMA_LPCG_I2C2_CLK 27 149 #define IMX_ADMA_LPCG_I2C3_CLK 28 150 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 151 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 152 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 153 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 154 #define IMX_ADMA_LPCG_FTM0_CLK 33 155 #define IMX_ADMA_LPCG_FTM1_CLK 34 156 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 157 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 158 #define IMX_ADMA_LPCG_PWM_HI_CLK 37 159 #define IMX_ADMA_LPCG_PWM_IPG_CLK 38 160 #define IMX_ADMA_LPCG_LCD_PIX_CLK 39 161 #define IMX_ADMA_LPCG_LCD_APB_CLK 40 162 #define IMX_ADMA_LPCG_DSP_ADB_CLK 41 163 #define IMX_ADMA_LPCG_DSP_IPG_CLK 42 164 #define IMX_ADMA_LPCG_DSP_CORE_CLK 43 165 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 166 167 #define IMX_ADMA_LPCG_CLK_END 45 168 169 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ 170
Indexes created Mon Oct 06 15:09:44 GMT 2025