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    Searched defs:INTC_WRITE (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/arm/gemini/
gemini_icu.c 61 #define INTC_WRITE(sc, o, v) \
126 INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
132 INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR,
143 INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
149 INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR,
201 INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, sc->sc_enabled_mask);
202 INTC_WRITE(sc, GEMINI_ICU_IRQ_CLEAR, irq_mask);
222 INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGMODE, sc->sc_edge_mask);
223 INTC_WRITE(sc, GEMINI_ICU_IRQ_TRIGLEVEL,
259 INTC_WRITE(sc, GEMINI_ICU_IRQ_ENABLE, 0)
    [all...]
  /src/sys/arch/arm/imx/
imx31_icu.c 78 #define INTC_WRITE(avic, reg, val) \
89 INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask);
91 INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask);
98 INTC_WRITE(avic, IMX31_INTENNUM, irq_base);
109 INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask);
111 INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask);
118 INTC_WRITE(avic, IMX31_INTDISNUM, irq_base);
139 INTC_WRITE(avic, priority_reg, v);
187 INTC_WRITE(avic, IMX31_NIMASK, ipl);
199 INTC_WRITE(avic, IMX31_NIMASK, saved_nimask)
    [all...]
imx51_tzic.c 92 #define INTC_WRITE(tzic, reg, val) \
176 INTC_WRITE(tzic, TZIC_ENSET(group), irq_mask);
187 INTC_WRITE(tzic, TZIC_ENCLEAR(group), irq_mask);
227 INTC_WRITE(tzic, TZIC_PRIORITY(priority_offset), reg);
267 INTC_WRITE(tzic, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
269 INTC_WRITE(tzic, TZIC_PRIOMASK, SW_TO_HW_IPL(IPL_NONE));
272 INTC_WRITE(tzic, TZIC_SYNCCTRL, 0x00);
277 INTC_WRITE(tzic, TZIC_INTSEC(i), 0xffffffff);
281 INTC_WRITE(tzic, TZIC_ENCLEAR(i), 0xffffffff);
  /src/sys/arch/arm/sunxi/
sunxi_intc.c 88 #define INTC_WRITE(sc, reg, val) \
99 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
100 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
110 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]);
111 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]);
190 INTC_WRITE(sc, INTC_IRQ_PEND_REG(group), pend);
253 INTC_WRITE(sc, INTC_EN_REG(i), 0);
254 INTC_WRITE(sc, INTC_MASK_REG(i), ~0U);
255 INTC_WRITE(sc, INTC_IRQ_PEND_REG(i),
259 INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN)
    [all...]
  /src/sys/arch/arm/ti/
ti_omapintc.c 69 #define INTC_WRITE(sc, g, o, v) \
114 INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask);
117 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
126 INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask);
163 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR);
260 INTC_WRITE(sc, n, INTC_MIR_SET, 0xffffffff);

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