1 /* $NetBSD: ti_omapintc.c,v 1.9 2022/02/11 23:48:33 riastradh Exp $ */ 2 /* 3 * Define the SDP2430 specific information and then include the generic OMAP 4 * interrupt header. 5 */ 6 7 /* 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain this list of conditions 12 * and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce this list of conditions 14 * and the following disclaimer in the documentation and/or other materials 15 * provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 19 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ti_omapintc.c,v 1.9 2022/02/11 23:48:33 riastradh Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/evcnt.h> 36 #include <sys/device.h> 37 #include <sys/kmem.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <machine/intr.h> 42 #include <sys/bus.h> 43 44 #include <arm/cpu.h> 45 #include <arm/armreg.h> 46 #include <arm/cpufunc.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #define INTC_CONTROL 0x048 51 #define INTC_CONTROL_NEWIRQAGR __BIT(0) 52 #define INTC_ITR 0x080 53 #define INTC_MIR 0x084 54 #define INTC_MIR_CLEAR 0x088 55 #define INTC_MIR_SET 0x08c 56 #define INTC_PENDING_IRQ 0x098 57 58 #define INTC_MAX_SOURCES 128 59 60 static const struct device_compatible_entry compat_data[] = { 61 /* compatible number of banks */ 62 { .compat = "ti,omap3-intc", .value = 3 }, 63 { .compat = "ti,am33xx-intc", .value = 4 }, 64 DEVICE_COMPAT_EOL 65 }; 66 67 #define INTC_READ(sc, g, o) \ 68 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o)) 69 #define INTC_WRITE(sc, g, o, v) \ 70 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o), v) 71 72 static int omap2icu_match(device_t, cfdata_t, void *); 73 static void omap2icu_attach(device_t, device_t, void *); 74 75 static void omap2icu_unblock_irqs(struct pic_softc *, size_t, uint32_t); 76 static void omap2icu_block_irqs(struct pic_softc *, size_t, uint32_t); 77 static void omap2icu_establish_irq(struct pic_softc *, struct intrsource *); 78 static void omap2icu_set_priority(struct pic_softc *, int); 79 #if 0 80 static void omap2icu_source_name(struct pic_softc *, int, char *, size_t); 81 #endif 82 83 static const struct pic_ops omap2icu_picops = { 84 .pic_unblock_irqs = omap2icu_unblock_irqs, 85 .pic_block_irqs = omap2icu_block_irqs, 86 .pic_establish_irq = omap2icu_establish_irq, 87 .pic_set_priority = omap2icu_set_priority, 88 #if 0 89 .pic_source_name = omap2icu_source_name, 90 #endif 91 }; 92 93 #define PICTOSOFTC(pic) \ 94 ((struct omap2icu_softc *)((uintptr_t)(pic) - offsetof(struct omap2icu_softc, sc_pic))) 95 96 struct omap2icu_softc { 97 device_t sc_dev; 98 bus_space_tag_t sc_memt; 99 bus_space_handle_t sc_memh; 100 struct pic_softc sc_pic; 101 uint32_t *sc_enabled_irqs; 102 u_int sc_nbank; 103 }; 104 105 static struct omap2icu_softc *intc_softc; 106 107 static void 108 omap2icu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 109 { 110 struct omap2icu_softc * const sc = PICTOSOFTC(pic); 111 const size_t group = irqbase / 32; 112 KASSERT((irq_mask & sc->sc_enabled_irqs[group]) == 0); 113 sc->sc_enabled_irqs[group] |= irq_mask; 114 INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask); 115 116 /* Force INTC to recompute IRQ availability */ 117 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR); 118 } 119 120 static void 121 omap2icu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 122 { 123 struct omap2icu_softc * const sc = PICTOSOFTC(pic); 124 const size_t group = irqbase / 32; 125 126 INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask); 127 sc->sc_enabled_irqs[group] &= ~irq_mask; 128 } 129 130 /* 131 * Called with interrupts disabled 132 */ 133 static int 134 find_pending_irqs(struct omap2icu_softc *sc, size_t group) 135 { 136 uint32_t pending = INTC_READ(sc, group, INTC_PENDING_IRQ); 137 138 KASSERT((sc->sc_enabled_irqs[group] & pending) == pending); 139 140 if (pending == 0) 141 return 0; 142 143 return pic_mark_pending_sources(&sc->sc_pic, group * 32, pending); 144 } 145 146 static void 147 omap_irq_handler(void *frame) 148 { 149 struct cpu_info * const ci = curcpu(); 150 struct omap2icu_softc * const sc = intc_softc; 151 const int oldipl = ci->ci_cpl; 152 const uint32_t oldipl_mask = __BIT(oldipl); 153 int ipl_mask = 0, n; 154 155 ci->ci_data.cpu_nintr++; 156 157 for (n = 0; n < sc->sc_nbank; n++) { 158 if (sc->sc_enabled_irqs[n]) 159 ipl_mask |= find_pending_irqs(sc, n); 160 } 161 162 /* force INTC to recompute IRQ */ 163 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR); 164 165 /* 166 * Record the pending_ipls and deliver them if we can. 167 */ 168 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 169 pic_do_pending_ints(I32_bit, oldipl, frame); 170 } 171 172 void 173 omap2icu_establish_irq(struct pic_softc *pic, struct intrsource *is) 174 { 175 KASSERT(is->is_irq < PICTOSOFTC(pic)->sc_pic.pic_maxsources); 176 KASSERT(is->is_type == IST_LEVEL); 177 } 178 179 static void 180 omap2icu_set_priority(struct pic_softc *pic, int ipl) 181 { 182 curcpu()->ci_cpl = ipl; 183 } 184 185 static void * 186 omapintc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 187 int (*func)(void *), void *arg, const char *xname) 188 { 189 const u_int irq = be32toh(specifier[0]); 190 if (irq >= INTC_MAX_SOURCES) { 191 device_printf(dev, "IRQ %u is invalid\n", irq); 192 return NULL; 193 } 194 195 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 196 return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, func, arg, 197 xname); 198 } 199 200 static void 201 omapintc_fdt_disestablish(device_t dev, void *ih) 202 { 203 intr_disestablish(ih); 204 } 205 206 static bool 207 omapintc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 208 { 209 if (!specifier) 210 return false; 211 212 const u_int irq = be32toh(specifier[0]); 213 snprintf(buf, buflen, "INTC irq %d", irq); 214 return true; 215 } 216 217 static const struct fdtbus_interrupt_controller_func omapintc_fdt_funcs = { 218 .establish = omapintc_fdt_establish, 219 .disestablish = omapintc_fdt_disestablish, 220 .intrstr = omapintc_fdt_intrstr, 221 }; 222 223 int 224 omap2icu_match(device_t parent, cfdata_t cf, void *aux) 225 { 226 struct fdt_attach_args * const faa = aux; 227 228 return of_compatible_match(faa->faa_phandle, compat_data); 229 } 230 231 void 232 omap2icu_attach(device_t parent, device_t self, void *aux) 233 { 234 struct omap2icu_softc * const sc = device_private(self); 235 struct fdt_attach_args * const faa = aux; 236 const int phandle = faa->faa_phandle; 237 bus_addr_t addr; 238 bus_size_t size; 239 int error, n; 240 241 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 242 aprint_error(": couldn't get registers\n"); 243 return; 244 } 245 246 sc->sc_dev = self; 247 sc->sc_memt = faa->faa_bst; 248 if (bus_space_map(sc->sc_memt, addr, size, 0, &sc->sc_memh) != 0) { 249 aprint_error(": couldn't map registers\n"); 250 return; 251 } 252 sc->sc_nbank = of_compatible_lookup(phandle, compat_data)->value; 253 sc->sc_enabled_irqs = 254 kmem_zalloc(sizeof(*sc->sc_enabled_irqs) * sc->sc_nbank, KM_SLEEP); 255 256 aprint_naive("\n"); 257 aprint_normal("\n"); 258 259 for (n = 0; n < sc->sc_nbank; n++) 260 INTC_WRITE(sc, n, INTC_MIR_SET, 0xffffffff); 261 262 sc->sc_dev = self; 263 264 sc->sc_pic.pic_ops = &omap2icu_picops; 265 sc->sc_pic.pic_maxsources = sc->sc_nbank * 32; 266 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 267 pic_add(&sc->sc_pic, 0); 268 error = fdtbus_register_interrupt_controller(self, phandle, 269 &omapintc_fdt_funcs); 270 if (error) { 271 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 272 error); 273 return; 274 } 275 276 KASSERT(intc_softc == NULL); 277 intc_softc = sc; 278 arm_fdt_irq_set_handler(omap_irq_handler); 279 } 280 281 CFATTACH_DECL_NEW(omapintc, 282 sizeof(struct omap2icu_softc), 283 omap2icu_match, omap2icu_attach, 284 NULL, NULL); 285
Indexes created Sat Sep 20 22:09:52 GMT 2025