1 /* $NetBSD: zs.c,v 1.84 2026/11/08 19:51:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.84 2026/11/08 19:51:13 thorpej Exp $"); 42 43 #include "opt_ddb.h" 44 #include "opt_kgdb.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/file.h> 51 #include <sys/ioctl.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> 54 #include <sys/tty.h> 55 #include <sys/time.h> 56 #include <sys/syslog.h> 57 #include <sys/intr.h> 58 59 #include <machine/autoconf.h> 60 #include <machine/openfirm.h> 61 #include <machine/cpu.h> 62 #include <machine/eeprom.h> 63 #include <machine/psl.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 #include <dev/sun/kbd_ms_ttyvar.h> 69 70 #include <dev/sbus/sbusvar.h> 71 #include <sparc64/dev/fhcvar.h> 72 #include <sparc64/dev/cons.h> 73 74 #include "ioconf.h" 75 #include "kbd.h" /* NKBD */ 76 #include "ms.h" /* NMS */ 77 #include "zs.h" /* NZS */ 78 79 /* Make life easier for the initialized arrays here. */ 80 #if NZS < 3 81 #undef NZS 82 #define NZS 3 83 #endif 84 85 /* 86 * Some warts needed by z8530tty.c - 87 * The default parity REALLY needs to be the same as the PROM uses, 88 * or you can not see messages done with printf during boot-up... 89 */ 90 int zs_def_cflag = (CREAD | CS8 | HUPCL); 91 92 /* 93 * The Sun provides a 4.9152 MHz clock to the ZS chips. 94 */ 95 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 96 97 #define ZS_DELAY() 98 99 /* The layout of this is hardware-dependent (padding, order). */ 100 struct zschan { 101 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 102 uint8_t zc_xxx0; 103 volatile uint8_t zc_data; /* data */ 104 uint8_t zc_xxx1; 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 /* ZS channel used as the console device (if any) */ 113 void *zs_conschan_get, *zs_conschan_put; 114 115 /* Saved PROM mappings */ 116 static struct zsdevice *zsaddr[NZS]; 117 118 static uint8_t zs_init_reg[16] = { 119 0, /* 0: CMD (reset, etc.) */ 120 0, /* 1: No interrupts yet. */ 121 0, /* 2: IVECT */ 122 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 123 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 124 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 125 0, /* 6: TXSYNC/SYNCLO */ 126 0, /* 7: RXSYNC/SYNCHI */ 127 0, /* 8: alias for data port */ 128 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 129 0, /*10: Misc. TX/RX control bits */ 130 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 131 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 132 0, /*13: BAUDHI (default=9600) */ 133 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 134 ZSWR15_BREAK_IE, 135 }; 136 137 /* Console ops */ 138 static int zscngetc(dev_t); 139 static void zscnputc(dev_t, int); 140 static void zscnpollc(dev_t, int); 141 142 struct consdev zs_consdev = { 143 .cn_getc = zscngetc, 144 .cn_putc = zscnputc, 145 .cn_pollc = zscnpollc, 146 }; 147 148 149 /**************************************************************** 150 * Autoconfig 151 ****************************************************************/ 152 153 /* Definition of the driver for autoconfig. */ 154 static int zs_match_sbus(device_t, cfdata_t, void *); 155 static void zs_attach_sbus(device_t, device_t, void *); 156 157 static int zs_match_fhc(device_t, cfdata_t, void *); 158 static void zs_attach_fhc(device_t, device_t, void *); 159 160 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 161 static int zs_print(void *, const char *); 162 163 CFATTACH_DECL_NEW(zs, sizeof(struct zsc_softc), 164 zs_match_sbus, zs_attach_sbus, NULL, NULL); 165 166 CFATTACH_DECL_NEW(zs_fhc, sizeof(struct zsc_softc), 167 zs_match_fhc, zs_attach_fhc, NULL, NULL); 168 169 /* Interrupt handlers. */ 170 int zscheckintr(void *); 171 static int zshard(void *); 172 static void zssoft(void *); 173 174 static int zs_get_speed(struct zs_chanstate *); 175 176 /* Console device support */ 177 static int zs_console_flags(int, int, int); 178 179 /* Power management hooks */ 180 int zs_enable(struct zs_chanstate *); 181 void zs_disable(struct zs_chanstate *); 182 183 /* from dev/ic/z8530tty.c */ 184 struct tty *zstty_get_tty_from_dev(device_t); 185 186 /* 187 * Is the zs chip present? 188 */ 189 static int 190 zs_match_sbus(device_t parent, cfdata_t cf, void *aux) 191 { 192 struct sbus_attach_args *sa = aux; 193 194 if (strcmp(cf->cf_name, sa->sa_name) != 0) 195 return (0); 196 197 return (1); 198 } 199 200 static int 201 zs_match_fhc(device_t parent, cfdata_t cf, void *aux) 202 { 203 struct fhc_attach_args *fa = aux; 204 205 if (strcmp(cf->cf_name, fa->fa_name) != 0) 206 return (0); 207 208 return (1); 209 } 210 211 static void 212 zs_attach_sbus(device_t parent, device_t self, void *aux) 213 { 214 struct zsc_softc *zsc = device_private(self); 215 struct sbus_attach_args *sa = aux; 216 bus_space_handle_t bh; 217 int zs_unit; 218 219 zsc->zsc_dev = self; 220 zs_unit = device_unit(self); 221 222 if (sa->sa_nintr == 0) { 223 aprint_error(": no interrupt lines\n"); 224 return; 225 } 226 227 /* Use the mapping setup by the Sun PROM if possible. */ 228 if (zsaddr[zs_unit] == NULL) { 229 /* Only map registers once. */ 230 if (sa->sa_npromvaddrs) { 231 /* 232 * We're converting from a 32-bit pointer to a 64-bit 233 * pointer. Since the 32-bit entity is negative, but 234 * the kernel is still mapped into the lower 4GB 235 * range, this needs to be zero-extended. 236 * 237 * XXXXX If we map the kernel and devices into the 238 * high 4GB range, this needs to be changed to 239 * sign-extend the address. 240 */ 241 sparc_promaddr_to_handle(sa->sa_bustag, 242 sa->sa_promvaddrs[0], &bh); 243 244 } else { 245 246 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 247 sa->sa_offset, 248 sa->sa_size, 249 BUS_SPACE_MAP_LINEAR, 250 &bh) != 0) { 251 aprint_error(": cannot map registers\n"); 252 return; 253 } 254 } 255 zsaddr[zs_unit] = bus_space_vaddr(sa->sa_bustag, bh); 256 } 257 zsc->zsc_bustag = sa->sa_bustag; 258 zsc->zsc_dmatag = sa->sa_dmatag; 259 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 260 zsc->zsc_node = sa->sa_node; 261 aprint_normal("\n"); 262 zs_attach(zsc, zsaddr[zs_unit], sa->sa_pri); 263 } 264 265 static void 266 zs_attach_fhc(device_t parent, device_t self, void *aux) 267 { 268 struct zsc_softc *zsc = device_private(self); 269 struct fhc_attach_args *fa = aux; 270 bus_space_handle_t bh; 271 int zs_unit; 272 273 zsc->zsc_dev = self; 274 zs_unit = device_unit(self); 275 276 if (fa->fa_nreg < 1 && fa->fa_npromvaddrs < 1) { 277 printf(": no registers\n"); 278 return; 279 } 280 281 if (fa->fa_nintr == 0) { 282 aprint_error(": no interrupt lines\n"); 283 return; 284 } 285 286 /* Use the mapping setup by the Sun PROM if possible. */ 287 if (zsaddr[zs_unit] == NULL) { 288 /* Only map registers once. */ 289 if (fa->fa_npromvaddrs) { 290 /* 291 * We're converting from a 32-bit pointer to a 64-bit 292 * pointer. Since the 32-bit entity is negative, but 293 * the kernel is still mapped into the lower 4GB 294 * range, this needs to be zero-extended. 295 * 296 * XXXXX If we map the kernel and devices into the 297 * high 4GB range, this needs to be changed to 298 * sign-extend the address. 299 */ 300 sparc_promaddr_to_handle(fa->fa_bustag, 301 fa->fa_promvaddrs[0], &bh); 302 303 } else { 304 305 if (fhc_bus_map(fa->fa_bustag, 306 fa->fa_reg[0].fbr_slot, 307 fa->fa_reg[0].fbr_offset, 308 fa->fa_reg[0].fbr_size, 309 BUS_SPACE_MAP_LINEAR, 310 &bh) != 0) { 311 aprint_error(": cannot map registers\n"); 312 return; 313 } 314 } 315 zsaddr[zs_unit] = bus_space_vaddr(fa->fa_bustag, bh); 316 } 317 zsc->zsc_bustag = fa->fa_bustag; 318 zsc->zsc_dmatag = NULL; 319 zsc->zsc_promunit = prom_getpropint(fa->fa_node, "slave", -2); 320 zsc->zsc_node = fa->fa_node; 321 aprint_normal("\n"); 322 zs_attach(zsc, zsaddr[zs_unit], fa->fa_intr[0]); 323 } 324 325 /* 326 * Attach a found zs. 327 * 328 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 329 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 330 */ 331 static void 332 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 333 { 334 struct zsc_attach_args zsc_args; 335 struct zs_chanstate *cs; 336 int channel; 337 338 if (zsd == NULL) { 339 aprint_error(": configuration incomplete\n"); 340 return; 341 } 342 343 /* 344 * Initialize software state for each channel. 345 */ 346 for (channel = 0; channel < 2; channel++) { 347 struct zschan *zc; 348 device_t child; 349 350 zsc_args.channel = channel; 351 cs = &zsc->zsc_cs_store[channel]; 352 zsc->zsc_cs[channel] = cs; 353 354 zs_lock_init(cs); 355 cs->cs_channel = channel; 356 cs->cs_private = NULL; 357 cs->cs_ops = &zsops_null; 358 cs->cs_brg_clk = PCLK / 16; 359 360 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 361 362 zsc_args.consdev = NULL; 363 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 364 zsc->zsc_node, 365 channel); 366 367 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 368 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 369 zsc_args.consdev = &zs_consdev; 370 } 371 372 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 373 zs_conschan_get = zc; 374 } 375 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 376 zs_conschan_put = zc; 377 } 378 379 /* Children need to set cn_dev, etc */ 380 cs->cs_reg_csr = &zc->zc_csr; 381 cs->cs_reg_data = &zc->zc_data; 382 383 memcpy(cs->cs_creg, zs_init_reg, 16); 384 memcpy(cs->cs_preg, zs_init_reg, 16); 385 386 /* XXX: Consult PROM properties for this?! */ 387 cs->cs_defspeed = zs_get_speed(cs); 388 cs->cs_defcflag = zs_def_cflag; 389 390 /* Make these correspond to cs_defcflag (-crtscts) */ 391 cs->cs_rr0_dcd = ZSRR0_DCD; 392 cs->cs_rr0_cts = 0; 393 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 394 cs->cs_wr5_rts = 0; 395 396 /* 397 * Clear the master interrupt enable. 398 * The INTENA is common to both channels, 399 * so just do it on the A channel. 400 */ 401 if (channel == 0) { 402 zs_write_reg(cs, 9, 0); 403 } 404 405 /* 406 * Look for a child driver for this channel. 407 * The child attach will setup the hardware. 408 */ 409 child = config_found(zsc->zsc_dev, (void *)&zsc_args, 410 zs_print, CFARGS_NONE); 411 if (child == NULL) { 412 /* No sub-driver. Just reset it. */ 413 uint8_t reset = (channel == 0) ? 414 ZSWR9_A_RESET : ZSWR9_B_RESET; 415 zs_lock_chan(cs); 416 zs_write_reg(cs, 9, reset); 417 zs_unlock_chan(cs); 418 } 419 #if (NKBD > 0) || (NMS > 0) 420 /* 421 * If this was a zstty it has a keyboard 422 * property on it we need to attach the 423 * sunkbd and sunms line disciplines. 424 */ 425 if (child 426 && (device_is_a(child, "zstty")) 427 && (prom_getproplen(zsc->zsc_node, "keyboard") == 0)) { 428 struct kbd_ms_tty_attach_args kma; 429 struct tty *tp; 430 431 kma.kmta_tp = tp = zstty_get_tty_from_dev(child); 432 kma.kmta_dev = tp->t_dev; 433 kma.kmta_consdev = zsc_args.consdev; 434 435 /* Attach 'em if we got 'em. */ 436 #if (NKBD > 0) 437 if (channel == 0) { 438 kma.kmta_name = "keyboard"; 439 config_found(child, (void *)&kma, NULL, 440 CFARGS_NONE); 441 } 442 #endif 443 #if (NMS > 0) 444 if (channel == 1) { 445 kma.kmta_name = "mouse"; 446 config_found(child, (void *)&kma, NULL, 447 CFARGS_NONE); 448 } 449 #endif 450 } 451 #endif 452 } 453 454 /* 455 * Now safe to install interrupt handlers. Note the arguments 456 * to the interrupt handlers aren't used. Note, we only do this 457 * once since both SCCs interrupt at the same level and vector. 458 */ 459 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc); 460 if (!(zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL, zssoft, zsc))) 461 panic("zsattach: could not establish soft interrupt"); 462 463 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 464 device_xname(zsc->zsc_dev), "intr"); 465 466 467 /* 468 * Set the master interrupt enable and interrupt vector. 469 * (common to both channels, do it on A) 470 */ 471 cs = zsc->zsc_cs[0]; 472 zs_lock_chan(cs); 473 /* interrupt vector */ 474 zs_write_reg(cs, 2, zs_init_reg[2]); 475 /* master interrupt control (enable) */ 476 zs_write_reg(cs, 9, zs_init_reg[9]); 477 zs_unlock_chan(cs); 478 } 479 480 static int 481 zs_print(void *aux, const char *name) 482 { 483 struct zsc_attach_args *args = aux; 484 485 if (name != NULL) 486 aprint_normal("%s: ", name); 487 488 if (args->channel != -1) 489 aprint_normal(" channel %d", args->channel); 490 491 return (UNCONF); 492 } 493 494 static int 495 zshard(void *arg) 496 { 497 struct zsc_softc *zsc = arg; 498 int rr3, rval; 499 500 rval = 0; 501 while ((rr3 = zsc_intr_hard(zsc))) { 502 /* Count up the interrupts. */ 503 rval |= rr3; 504 zsc->zsc_intrcnt.ev_count++; 505 } 506 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 507 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 508 zsc->zsc_softintr) { 509 softint_schedule(zsc->zsc_softintr); 510 } 511 return (rval); 512 } 513 514 int 515 zscheckintr(void *arg) 516 { 517 struct zsc_softc *zsc; 518 int unit, rval; 519 520 rval = 0; 521 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 522 523 zsc = device_lookup_private(&zs_cd, unit); 524 if (zsc == NULL) 525 continue; 526 rval = (zshard((void *)zsc) || rval); 527 } 528 return (rval); 529 } 530 531 532 static void 533 zssoft(void *arg) 534 { 535 struct zsc_softc *zsc = arg; 536 537 #if 0 /* not yet */ 538 /* Make sure we call the tty layer with ttylock held. */ 539 ttylock(tp); 540 #endif 541 (void)zsc_intr_soft(zsc); 542 #if 0 /* not yet */ 543 ttyunlock(tp); 544 #endif 545 } 546 547 548 /* 549 * Compute the current baud rate given a ZS channel. 550 */ 551 static int 552 zs_get_speed(struct zs_chanstate *cs) 553 { 554 int tconst; 555 556 tconst = zs_read_reg(cs, 12); 557 tconst |= zs_read_reg(cs, 13) << 8; 558 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 559 } 560 561 /* 562 * MD functions for setting the baud rate and control modes. 563 */ 564 int 565 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */) 566 { 567 int tconst, real_bps; 568 569 if (bps == 0) 570 return (0); 571 572 #ifdef DIAGNOSTIC 573 if (cs->cs_brg_clk == 0) 574 panic("zs_set_speed"); 575 #endif 576 577 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 578 if (tconst < 0) 579 return (EINVAL); 580 581 /* Convert back to make sure we can do it. */ 582 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 583 584 /* XXX - Allow some tolerance here? */ 585 if (real_bps != bps) 586 return (EINVAL); 587 588 cs->cs_preg[12] = tconst; 589 cs->cs_preg[13] = tconst >> 8; 590 591 /* Caller will stuff the pending registers. */ 592 return (0); 593 } 594 595 int 596 zs_set_modes(struct zs_chanstate *cs, int cflag) 597 { 598 599 /* 600 * Output hardware flow control on the chip is horrendous: 601 * if carrier detect drops, the receiver is disabled, and if 602 * CTS drops, the transmitter is stopped IN MID CHARACTER! 603 * Therefore, NEVER set the HFC bit, and instead use the 604 * status interrupt to detect CTS changes. 605 */ 606 zs_lock_chan(cs); 607 cs->cs_rr0_pps = 0; 608 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 609 cs->cs_rr0_dcd = 0; 610 if ((cflag & MDMBUF) == 0) 611 cs->cs_rr0_pps = ZSRR0_DCD; 612 } else 613 cs->cs_rr0_dcd = ZSRR0_DCD; 614 if ((cflag & CRTSCTS) != 0) { 615 cs->cs_wr5_dtr = ZSWR5_DTR; 616 cs->cs_wr5_rts = ZSWR5_RTS; 617 cs->cs_rr0_cts = ZSRR0_CTS; 618 } else if ((cflag & CDTRCTS) != 0) { 619 cs->cs_wr5_dtr = 0; 620 cs->cs_wr5_rts = ZSWR5_DTR; 621 cs->cs_rr0_cts = ZSRR0_CTS; 622 } else if ((cflag & MDMBUF) != 0) { 623 cs->cs_wr5_dtr = 0; 624 cs->cs_wr5_rts = ZSWR5_DTR; 625 cs->cs_rr0_cts = ZSRR0_DCD; 626 } else { 627 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 628 cs->cs_wr5_rts = 0; 629 cs->cs_rr0_cts = 0; 630 } 631 zs_unlock_chan(cs); 632 633 /* Caller will stuff the pending registers. */ 634 return (0); 635 } 636 637 638 /* 639 * Read or write the chip with suitable delays. 640 */ 641 642 u_char 643 zs_read_reg(struct zs_chanstate *cs, u_char reg) 644 { 645 u_char val; 646 647 *cs->cs_reg_csr = reg; 648 ZS_DELAY(); 649 val = *cs->cs_reg_csr; 650 ZS_DELAY(); 651 return (val); 652 } 653 654 void 655 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 656 { 657 *cs->cs_reg_csr = reg; 658 ZS_DELAY(); 659 *cs->cs_reg_csr = val; 660 ZS_DELAY(); 661 } 662 663 u_char 664 zs_read_csr(struct zs_chanstate *cs) 665 { 666 u_char val; 667 668 val = *cs->cs_reg_csr; 669 ZS_DELAY(); 670 return (val); 671 } 672 673 void 674 zs_write_csr(struct zs_chanstate *cs, u_char val) 675 { 676 *cs->cs_reg_csr = val; 677 ZS_DELAY(); 678 } 679 680 u_char 681 zs_read_data(struct zs_chanstate *cs) 682 { 683 u_char val; 684 685 val = *cs->cs_reg_data; 686 ZS_DELAY(); 687 return (val); 688 } 689 690 void 691 zs_write_data(struct zs_chanstate *cs, u_char val) 692 { 693 *cs->cs_reg_data = val; 694 ZS_DELAY(); 695 } 696 697 /**************************************************************** 698 * Console support functions (Sun specific!) 699 * Note: this code is allowed to know about the layout of 700 * the chip registers, and uses that to keep things simple. 701 * XXX - I think I like the mvme167 code better. -gwr 702 ****************************************************************/ 703 704 extern void Debugger(void); 705 706 /* 707 * Handle user request to enter kernel debugger. 708 */ 709 void 710 zs_abort(void) 711 { 712 volatile struct zschan *zc = zs_conschan_get; 713 int rr0; 714 715 /* Wait for end of break to avoid PROM abort. */ 716 /* XXX - Limit the wait? */ 717 do { 718 rr0 = zc->zc_csr; 719 ZS_DELAY(); 720 } while (rr0 & ZSRR0_BREAK); 721 722 #if defined(KGDB) 723 zskgdb(); 724 #elif defined(DDB) 725 if (!db_active) 726 Debugger(); 727 else 728 /* Debugger is probably hozed */ 729 callrom(); 730 #else 731 printf("stopping on keyboard abort\n"); 732 callrom(); 733 #endif 734 } 735 736 737 /* 738 * Polled input char. 739 */ 740 int 741 zs_getc(void *arg) 742 { 743 volatile struct zschan *zc = arg; 744 int s, c, rr0; 745 746 s = splhigh(); 747 /* Wait for a character to arrive. */ 748 do { 749 rr0 = zc->zc_csr; 750 ZS_DELAY(); 751 } while ((rr0 & ZSRR0_RX_READY) == 0); 752 753 c = zc->zc_data; 754 ZS_DELAY(); 755 splx(s); 756 757 /* 758 * This is used by the kd driver to read scan codes, 759 * so don't translate '\r' ==> '\n' here... 760 */ 761 return (c); 762 } 763 764 /* 765 * Polled output char. 766 */ 767 void 768 zs_putc(void *arg, int c) 769 { 770 volatile struct zschan *zc = arg; 771 int s, rr0; 772 773 s = splhigh(); 774 775 /* Wait for transmitter to become ready. */ 776 do { 777 rr0 = zc->zc_csr; 778 ZS_DELAY(); 779 } while ((rr0 & ZSRR0_TX_READY) == 0); 780 781 /* 782 * Send the next character. 783 * Now you'd think that this could be followed by a ZS_DELAY() 784 * just like all the other chip accesses, but it turns out that 785 * the `transmit-ready' interrupt isn't de-asserted until 786 * some period of time after the register write completes 787 * (more than a couple instructions). So to avoid stray 788 * interrupts we put in the 2us delay regardless of CPU model. 789 */ 790 zc->zc_data = c; 791 delay(2); 792 793 splx(s); 794 } 795 796 /*****************************************************************/ 797 798 799 800 801 /* 802 * Polled console input putchar. 803 */ 804 static int 805 zscngetc(dev_t dev) 806 { 807 return (zs_getc(zs_conschan_get)); 808 } 809 810 /* 811 * Polled console output putchar. 812 */ 813 static void 814 zscnputc(dev_t dev, int c) 815 { 816 zs_putc(zs_conschan_put, c); 817 } 818 819 int swallow_zsintrs; 820 821 static void 822 zscnpollc(dev_t dev, int on) 823 { 824 /* 825 * Need to tell zs driver to acknowledge all interrupts or we get 826 * annoying spurious interrupt messages. This is because mucking 827 * with spl() levels during polling does not prevent interrupts from 828 * being generated. 829 */ 830 831 if (on) swallow_zsintrs++; 832 else swallow_zsintrs--; 833 } 834 835 int 836 zs_console_flags(int promunit, int node, int channel) 837 { 838 int cookie, flags = 0; 839 char buf[255]; 840 841 /* 842 * We'll just do the OBP grovelling down here since that's 843 * the only type of firmware we support. 844 */ 845 846 /* Default to channel 0 if there are no explicit prom args */ 847 cookie = 0; 848 if (node == prom_instance_to_package(prom_stdin())) { 849 if (prom_getoption("input-device", buf, sizeof buf) == 0 && 850 strcmp("ttyb", buf) == 0) 851 cookie = 1; 852 853 if (channel == cookie) 854 flags |= ZS_HWFLAG_CONSOLE_INPUT; 855 } 856 857 if (node == prom_instance_to_package(prom_stdout())) { 858 if (prom_getoption("output-device", buf, sizeof buf) == 0 && 859 strcmp("ttyb", buf) == 0) 860 cookie = 1; 861 862 if (channel == cookie) 863 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 864 } 865 866 return (flags); 867 } 868 869
Indexes created Tue Nov 10 00:26:44 UTC 2026