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      1 /*	$NetBSD: ixm1200reg.h,v 1.2 2009/10/21 14:15:51 rmind Exp $ */
      2 /*
      3  * Copyright (c) 2002
      4  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _IXM1200REG_H_
     30 #define _IXM1200REG_H_
     31 
     32 /*
     33  * Memory map and register definitions for the Intel IXM1200
     34  * Evaluation Board.
     35  */
     36 
     37 /* Virtual address for SlowPort I/O space */
     38 #define IXM1200_SLOWPORT_VBASE	(IXP12X0_PCI_IO_VBASE + IXP12X0_PCI_IO_SIZE)
     39 					/* va=0xf0021000 */
     40 
     41 /*
     42  * Slow Port I/O
     43  */
     44 
     45 /* Status LEDs (4x2 bits) write-only */
     46 #define	IXM1200_LED_VADDR	IXM1200_SLOWPORT_VBASE
     47 #define	IXM1200_LED_ADDR_SIZE	0x1000
     48 #define	IXM1200_LED_ADDR	0x38508000
     49 
     50 /* Dip Switches (4 Bits) read-only */
     51 #define	IXM1200_DIP_VADDR	(IXM1200_SLOWPORT_VBASE + IXM1200_LED_VADDR_SIZE)
     52 #define	IXM1200_DIP_ADDR_SIZE	0x1000
     53 #define	IXM1200_DIP_ADDR	0x38509000
     54 
     55 /* Board Revision, read-only */
     56 #define	IXM1200_REV_ADDR	0x3850A000
     57 
     58 /* SDRAM Address Width, read-only */
     59 #define	IXM1200_SDRAM_WIDTH	0x3850B000
     60 
     61 /* MAC0(IXF440 Multiport 10/100Mbps Ethernet Cont. ) */
     62 
     63 /* PCI Configuration Cycles */
     64 #define	IXM1200_PCI_CYCLE_SIZE	0x00000100
     65 
     66 /* IXP1200, IDSEL=A11 */
     67 #define	IXM1200_CYCLE_ADDR	0x00000800
     68 #define	IXM1200_CYCLE_SIZE	IXM1200_PCI_CYCLE_SIZE
     69 
     70 /* PCIBridge, IDSEL=A12 */
     71 #define	IXM1200_PB_CYCLE_ADDR	0x00001000
     72 #define	IXM1200_PB_CYCLE_SIZE	IXM1200_PCI_CYCLE_SIZE
     73 
     74 /* Ether MAC/PHY, IDSEL=A13 */
     75 #define	IXM1200_MAC_CYCLE_ADDR	0x00002000
     76 #define	IXM1200_MAC_CYCLE_SIZE	IXM1200_PCI_CYCLE_SIZE
     77 
     78 /* PMC Expansion, IDSEL=A14 */
     79 #define	IXM1200_PMC_CYCLE_ADDR	0x00002000
     80 #define	IXM1200_MAC_CYCLE_SIZE	IXM1200_PCI_CYCLE_SIZE
     81 
     82 #endif /* _IXM1200REG_H_ */
     83