1 /* $NetBSD: brh_start.S,v 1.3 2014/01/13 18:26:34 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 39 #include <machine/asm.h> 40 #include <arm/armreg.h> 41 #include "assym.h" 42 43 #include <arm/xscale/beccreg.h> 44 45 #include <evbarm/adi_brh/brhreg.h> 46 47 RCSID("$NetBSD: brh_start.S,v 1.3 2014/01/13 18:26:34 matt Exp $") 48 49 .section .start,"ax",%progbits 50 51 .global _C_LABEL(brh_start) 52 _C_LABEL(brh_start): 53 /* 54 * Get a pointer to the LED (physical address). 55 */ 56 mov ip, #(BRH_LED_BASE) 57 58 /* 59 * We will go ahead and disable the MMU here so that we don't 60 * have to worry about flushing caches, etc. 61 * 62 * Note that we may not currently be running VA==PA, which means 63 * we'll need to leap to the next insn after disabing the MMU. 64 */ 65 adr r8, .Lunmapped 66 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 67 orr r8, r8, #0xc0000000 /* OR in physical base address */ 68 69 mrc p15, 0, r2, c1, c0, 0 70 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 71 mcr p15, 0, r2, c1, c0, 0 72 73 nop 74 nop 75 nop 76 77 mov pc, r8 /* Heave-ho! */ 78 79 .Lunmapped: 80 /* 81 * We want to construct a memory map that maps us 82 * VA==PA (SDRAM at 0xc0000000) (which also happens 83 * to be where the kernel address space starts). 84 * We create these mappings uncached and unbuffered 85 * to be safe. 86 * 87 * We also map various devices at their expected locations, 88 * because we will need to talk to them during bootstrap. 89 * 90 * We just use section mappings for all of this to make it easy. 91 * 92 * We will put the L1 table to do all this at 0xc0004000. 93 */ 94 95 96 /* 97 * Step 1: Map the entire address space VA==PA. 98 */ 99 ldr r0, .Ltable /* r0 = &l1table */ 100 101 mov r3, #(L1_S_AP_KRW) 102 orr r3, r3, #(L1_TYPE_S) 103 mov r2, #0x100000 /* advance by 1MB */ 104 mov r1, #0x1000 /* 4096MB */ 105 1: 106 str r3, [r0], #0x04 107 add r3, r3, r2 108 subs r1, r1, #1 109 bgt 1b 110 111 #if 0 112 /* 113 * Step 2: Map the PCI configuration space (this is needed 114 * to access some of the core logic registers). 115 */ 116 ldr r0, .Ltable /* r0 = &l1table */ 117 118 mov r3, #(L1_S_AP_KRW) 119 orr r3, r3, #(L1_TYPE_S) 120 orr r3, r3, #(BECC_PCI_CONF_BASE) 121 add r0, r0, #((BRH_PCI_CONF_VBASE >> L1_S_SHIFT) * 4) 122 mov r1, #(BRH_PCI_CONF_VSIZE >> L1_S_SHIFT) 123 1: 124 str r3, [r0], #0x04 125 add r3, r3, r2 126 subs r1, r1, #1 127 bgt 1b 128 #endif 129 130 /* 131 * Step 3: Map the BECC, UARTs, and LED display. 132 */ 133 ldr r0, .Ltable /* r0 = &l1table */ 134 135 mov r3, #(L1_S_AP_KRW) 136 orr r3, r3, #(L1_TYPE_S) 137 138 orr r3, r3, #(BECC_REG_BASE) 139 ldr r2, .Lbrh_becc_vbase 140 str r3, [r0, r2] 141 bic r3, r3, #(BECC_REG_BASE) 142 143 orr r3, r3, #(BRH_UART1_BASE) 144 ldr r2, .Lbrh_uart1_vbase 145 str r3, [r0, r2] 146 bic r3, r3, #(BRH_UART1_BASE) 147 148 orr r3, r3, #(BRH_UART2_BASE) 149 ldr r2, .Lbrh_uart2_vbase 150 str r3, [r0, r2] 151 bic r3, r3, #(BRH_UART2_BASE) 152 153 orr r3, r3, #(BRH_LED_BASE) 154 ldr r2, .Lbrh_led_vbase 155 str r3, [r0, r2] 156 bic r3, r3, #(BRH_LED_BASE) 157 158 /* OK! Page table is set up. Give it to the CPU. */ 159 ldr r0, .Ltable 160 mcr p15, 0, r0, c2, c0, 0 161 162 /* Flush the old TLBs, just in case. */ 163 mcr p15, 0, r0, c8, c7, 0 164 165 /* Set the Domain Access register. Very important! */ 166 mov r0, #1 167 mcr p15, 0, r0, c3, c0, 0 168 169 /* Get ready to jump to the "real" kernel entry point... */ 170 ldr r0, .Lstart 171 172 /* OK, let's enable the MMU. */ 173 mrc p15, 0, r2, c1, c0, 0 174 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 175 mcr p15, 0, r2, c1, c0, 0 176 177 nop 178 nop 179 nop 180 181 /* CPWAIT sequence to make sure the MMU is on... */ 182 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 183 mov r2, r2 /* force it to complete */ 184 mov pc, r0 /* leap to kernel entry point! */ 185 186 .Lbrh_becc_vbase: 187 .word ((BRH_BECC_VBASE >> L1_S_SHIFT) * 4) 188 189 .Lbrh_uart1_vbase: 190 .word ((BRH_UART1_VBASE >> L1_S_SHIFT) * 4) 191 192 .Lbrh_uart2_vbase: 193 .word ((BRH_UART2_VBASE >> L1_S_SHIFT) * 4) 194 195 .Lbrh_led_vbase: 196 .word ((BRH_LED_VBASE >> L1_S_SHIFT) * 4) 197 198 .Ltable: 199 .word 0xc0004000 200 201 .Lstart: 202 .word start 203
Indexes created Tue Oct 21 16:10:11 GMT 2025