1 /* $NetBSD: marvell,pxa910.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 #ifndef __DTS_MARVELL_PXA910_CLOCK_H 5 #define __DTS_MARVELL_PXA910_CLOCK_H 6 7 /* fixed clocks and plls */ 8 #define PXA910_CLK_CLK32 1 9 #define PXA910_CLK_VCTCXO 2 10 #define PXA910_CLK_PLL1 3 11 #define PXA910_CLK_PLL1_2 8 12 #define PXA910_CLK_PLL1_4 9 13 #define PXA910_CLK_PLL1_8 10 14 #define PXA910_CLK_PLL1_16 11 15 #define PXA910_CLK_PLL1_6 12 16 #define PXA910_CLK_PLL1_12 13 17 #define PXA910_CLK_PLL1_24 14 18 #define PXA910_CLK_PLL1_48 15 19 #define PXA910_CLK_PLL1_96 16 20 #define PXA910_CLK_PLL1_13 17 21 #define PXA910_CLK_PLL1_13_1_5 18 22 #define PXA910_CLK_PLL1_2_1_5 19 23 #define PXA910_CLK_PLL1_3_16 20 24 #define PXA910_CLK_PLL1_192 21 25 #define PXA910_CLK_UART_PLL 27 26 #define PXA910_CLK_USB_PLL 28 27 28 /* apb periphrals */ 29 #define PXA910_CLK_TWSI0 60 30 #define PXA910_CLK_TWSI1 61 31 #define PXA910_CLK_TWSI2 62 32 #define PXA910_CLK_TWSI3 63 33 #define PXA910_CLK_GPIO 64 34 #define PXA910_CLK_KPC 65 35 #define PXA910_CLK_RTC 66 36 #define PXA910_CLK_PWM0 67 37 #define PXA910_CLK_PWM1 68 38 #define PXA910_CLK_PWM2 69 39 #define PXA910_CLK_PWM3 70 40 #define PXA910_CLK_UART0 71 41 #define PXA910_CLK_UART1 72 42 #define PXA910_CLK_UART2 73 43 #define PXA910_CLK_SSP0 74 44 #define PXA910_CLK_SSP1 75 45 #define PXA910_CLK_TIMER0 76 46 #define PXA910_CLK_TIMER1 77 47 48 /* axi periphrals */ 49 #define PXA910_CLK_DFC 100 50 #define PXA910_CLK_SDH0 101 51 #define PXA910_CLK_SDH1 102 52 #define PXA910_CLK_SDH2 103 53 #define PXA910_CLK_USB 104 54 #define PXA910_CLK_SPH 105 55 #define PXA910_CLK_DISP0 106 56 #define PXA910_CLK_CCIC0 107 57 #define PXA910_CLK_CCIC0_PHY 108 58 #define PXA910_CLK_CCIC0_SPHY 109 59 60 #define PXA910_NR_CLKS 200 61 #endif 62
Indexes created Mon Oct 06 15:09:44 GMT 2025